diff options
author | satya priya <skakit@codeaurora.org> | 2019-09-19 16:45:18 +0530 |
---|---|---|
committer | Julius Werner <jwerner@chromium.org> | 2020-04-21 21:54:48 +0000 |
commit | 52353d09fc981c48b58ebf8bf44f18ad12e119d2 (patch) | |
tree | be52ac51d98777660af17ee5136803e51cb128b2 /src/soc/qualcomm/sc7180/Makefile.inc | |
parent | 47a0832f821ab0e005f3552d0a6a26624c78a0c0 (diff) |
sc7180: Add I2C driver
Add I2C functionality in coreboot.
Change-Id: I61221ffff8afe5c7ede5abb9e194e242ab0274d8
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36830
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/sc7180/Makefile.inc')
-rw-r--r-- | src/soc/qualcomm/sc7180/Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 4a931f4b9c..4961d244d0 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -8,6 +8,7 @@ bootblock-y += timer.c bootblock-y += spi.c bootblock-y += qupv3_spi.c bootblock-y += gpio.c +bootblock-y += qupv3_i2c.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c bootblock-y += clock.c bootblock-$(CONFIG_SC7180_QSPI) += qspi.c @@ -19,6 +20,7 @@ verstage-y += timer.c verstage-y += spi.c verstage-y += qupv3_spi.c verstage-y += gpio.c +verstage-y += qupv3_i2c.c verstage-y += clock.c verstage-$(CONFIG_SC7180_QSPI) += qspi.c verstage-y += qcom_qup_se.c @@ -36,6 +38,7 @@ romstage-y += usb.c romstage-y += spi.c romstage-y += qupv3_spi.c romstage-y += gpio.c +romstage-y += qupv3_i2c.c romstage-y += clock.c romstage-$(CONFIG_SC7180_QSPI) += qspi.c romstage-y += qcom_qup_se.c @@ -48,6 +51,7 @@ ramstage-y += timer.c ramstage-y += spi.c ramstage-y += qupv3_spi.c ramstage-y += gpio.c +ramstage-y += qupv3_i2c.c ramstage-y += clock.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ramstage-y += aop_load_reset.c |