diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/qualcomm/qcs405/usb.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/qcs405/usb.c')
| -rw-r--r-- | src/soc/qualcomm/qcs405/usb.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c index a94973ff2b..7ddfaa231e 100644 --- a/src/soc/qualcomm/qcs405/usb.c +++ b/src/soc/qualcomm/qcs405/usb.c @@ -183,16 +183,16 @@ static void hs_usb_phy_init(struct usb_dwc3_cfg *dwc3) static void setup_dwc3(struct usb_dwc3 *dwc3) { /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits_le32(&dwc3->usb3pipectl, + clrsetbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_DELAYP1TRANS, DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | DWC3_GCTL_DISSCRAMBLE), DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); /* configure controller in Host mode */ - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); printk(BIOS_INFO, "Configure USB in Host mode\n"); } @@ -213,10 +213,10 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) if (port == HSUSB_SS_PORT_0) { /* Set PHY reset. */ - setbits_le32(&dwc3->usb2_phy_bcr, BIT(1)); + setbits32(&dwc3->usb2_phy_bcr, BIT(1)); udelay(15); /* Clear PHY reset. */ - clrbits_le32(&dwc3->usb2_phy_bcr, BIT(1)); + clrbits32(&dwc3->usb2_phy_bcr, BIT(1)); } else { clock_reset_bcr(dwc3->usb2_phy_bcr, 1); udelay(15); @@ -229,13 +229,13 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) if (port == HSUSB_SS_PORT_0) { /* Set PHY POR reset. */ - setbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0)); + setbits32(&dwc3->usb2_phy_por_bcr, BIT(0)); val = read8(&dwc3->usb2_phy_dig->ctrl_common0); val &= ~(0x4); write8(&dwc3->usb2_phy_dig->ctrl_common0, val); udelay(20); /* Clear PHY POR reset. */ - clrbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0)); + clrbits32(&dwc3->usb2_phy_por_bcr, BIT(0)); } else { clock_reset_bcr(dwc3->usb2_phy_por_bcr, 1); val = read8(&dwc3->usb2_phy_dig->ctrl_common0); @@ -254,13 +254,13 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) */ /* Configure dwc3 to use UTMI clock as PIPE clock not present */ - setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, PIPE_UTMI_CLK_DIS); udelay(2); - setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); udelay(3); - clrbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + clrbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, PIPE_UTMI_CLK_DIS); printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); |