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| author | Yuchi Chen <yuchi.chen@intel.com> | 2024-11-08 14:18:08 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-11-19 10:33:03 +0000 |
| commit | 7cfdb3bc1a59280c1aeb2506e60384c42e05f6de (patch) | |
| tree | 1251152aa47a54c60320271c1690b8aa15592a3f /src/soc/qualcomm/qcs405/mmu.c | |
| parent | 26be949137e6ba7e5cf70b668731e7ef219ec283 (diff) | |
soc/intel/common/block/gpmr: Disable GPMR regs if ext-BIOS is disabled
General Purpose Memory Range registers are only used if extended BIOS
region is enabled now, this patch wraps the related code with Kconfig
item `CONFIG_FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW`.
Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src/soc/qualcomm/qcs405/mmu.c')
0 files changed, 0 insertions, 0 deletions