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| author | Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com> | 2019-12-03 16:12:13 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-16 09:36:49 +0000 |
| commit | 8d9262a7e7c0b9ec8a48aee9792cef2bd15667d2 (patch) | |
| tree | 78032679cb86947fc3957383d08f81c8ad3eedf4 /src/soc/qualcomm/qcs405/include | |
| parent | b7eb1097e5d38cbf7fd6ee6001cde264f1e74984 (diff) | |
soc/intel/tigerlake: Pick correct pmc base reg from pch type
Update PMC shadow register base address for Jasperlake
Correct PCH detection logic based on PCH ids and return correct base
address based on PCH detected since our code supports both tgl and jsl.
Change-Id: Iea3311b3dc8dc3ee5ea54db1148f386c2a5dd563
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/soc/qualcomm/qcs405/include')
0 files changed, 0 insertions, 0 deletions