diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-06-11 11:59:07 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-06-13 06:49:23 +0000 |
| commit | 46514c2b877c29c2d7c2061a9785736e270c0c62 (patch) | |
| tree | 2f78550192bce548139ef49fdac6623dad578703 /src/soc/qualcomm/qcs405/include | |
| parent | 00148bba7146318e2e815d8c13e33278f63814c9 (diff) | |
treewide: Add Kconfig variable MEMLAYOUT_LD_FILE
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows
SoC/mainboard to provide a linker file for the platform. x86 already
provides a default memlayout.ld under src/arch/x86. With this new
Kconfig variable, it is possible for the SoC/mainboard code for x86 to
provide a custom linker file as well.
Makefile.inc is updated for all architectures to use this new Kconfig
variable instead of assuming memlayout.ld files under a certain
path. All non-x86 boards used memlayout.ld under mainboard
directory. However, a lot of these boards were simply including the
memlayout from SoC. So, this change also updates these mainboards and
SoCs to define the Kconfig as required.
BUG=b:155322763
TEST=Verified that abuild with --timeless option results in the same
coreboot.rom image for all boards.
Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/qcs405/include')
| -rw-r--r-- | src/soc/qualcomm/qcs405/include/soc/memlayout.ld | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld deleted file mode 100644 index ff2ad2f99c..0000000000 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <memlayout.h> -#include <arch/header.ld> - -/* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */ -#define SSRAM_START(addr) SYMBOL(ssram, addr) -#define SSRAM_END(addr) SYMBOL(essram, addr) - -/* BOOT_IMEM : 0x8C00000 - 0x8D80000 */ -#define BSRAM_START(addr) SYMBOL(bsram, addr) -#define BSRAM_END(addr) SYMBOL(ebsram, addr) - -SECTIONS -{ - SSRAM_START(0x8600000) - SSRAM_END(0x8608000) - - BSRAM_START(0x8C00000) - OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K) - REGION(fw_reserved2, 0x8C19000, 0x16000, 4096) - BOOTBLOCK(0x8C2F000, 40K) - TTB(0x8C39000, 56K) - VBOOT2_WORK(0x8C47000, 12K) - STACK(0x8C4B000, 16K) - TIMESTAMP(0x8C4F000, 1K) - PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) - PRERAM_CBFS_CACHE(0x8C57400, 70K) - FMAP_CACHE(0x8C68C00, 2K) - REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100) - BSRAM_END(0x8D80000) - - DRAM_START(0x80000000) - /* DDR Carveout for BL31 usage */ - REGION(dram_reserved, 0x85000000, 0x5100000, 4096) - POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 128K) -} |