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authorRonald G Minnich <rminnich@gmail.com>2024-03-15 21:56:20 -0700
committerron minnich <rminnich@gmail.com>2024-03-22 23:01:48 +0000
commit200f7b7ee13b98d726bd0e5de2792a14c558a7ea (patch)
tree3df0dfd97c06196af2a2d92aef7e88912f088e4b /src/soc/qualcomm/qcs405/include
parent87fa1d07b57a8087da031e3db72695f0547db0c9 (diff)
arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFG
Older parts do not have the menvcfg csr. Provide a Kconfig variable, default y, to enable it. Check the variable in the payload code, when coreboot SBI is used, and print out if it is enabled. The SiFive FU540 and FU740 do not support this register; set the variable to n for those parts. Add constants for this new CSR. Change-Id: I6ea302a5acd98f6941bf314da89dd003ab20b596 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81425 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/qualcomm/qcs405/include')
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