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authorYu-Ping Wu <yupingso@chromium.org>2019-10-16 10:57:22 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-10-17 15:03:54 +0000
commit88ce8043c509b530909bbbd5f2778623c6872cdb (patch)
tree8d26f37bdd797977692859979534db2a1ed7c2a1 /src/soc/qualcomm/qcs405/gpio.c
parent5b29f17ef065fe3492ce3573dbefd037bd645c5b (diff)
soc/mediatek/mt8183: Fix DDR phy config number
Some typos are fixed to make DVFS switch work. BUG=b:142358843 BRANCH=kukui TEST=emerge-kukui coreboot Change-Id: I064d4a2c46187ac5780352da742bd56e82c22c14 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/qcs405/gpio.c')
0 files changed, 0 insertions, 0 deletions