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authorTaniya Das <tdas@codeaurora.org>2019-04-04 15:28:36 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-04-23 18:01:06 +0000
commit4b766393e2436bc678a4717043522a77cbddd2f8 (patch)
tree2b8d3e5240810f5e9a36bc94022ec2c68d3f77b3 /src/soc/qualcomm/qcs405/gpio.c
parent3ee485741bede7535377ef10516596524f8008a8 (diff)
qcs405: Add support of GPIO IRQ APIs
Add support of GPIO IRQ APIs. Change-Id: I11715a93999012622a5e28455731cbe249ba8f2c Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/qualcomm/qcs405/gpio.c')
-rw-r--r--src/soc/qualcomm/qcs405/gpio.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c
index 18aacf4ce4..7b2238d77f 100644
--- a/src/soc/qualcomm/qcs405/gpio.c
+++ b/src/soc/qualcomm/qcs405/gpio.c
@@ -71,3 +71,28 @@ void gpio_output(gpio_t gpio, int value)
gpio_configure(gpio, GPIO_FUNC_GPIO,
GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE);
}
+
+void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull)
+{
+ struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
+
+ gpio_configure(gpio, GPIO_FUNC_GPIO,
+ pull, GPIO_2MA, GPIO_DISABLE);
+
+ clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK <<
+ GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT);
+ clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE
+ << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE
+ << GPIO_INTR_RAW_STATUS_EN_SHIFT);
+}
+
+int gpio_irq_status(gpio_t gpio)
+{
+ struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
+
+ if (!(read32(&regs->intr_status) & GPIO_INTR_STATUS_MASK))
+ return 0;
+
+ write32(&regs->intr_status, GPIO_INTR_STATUS_DISABLE);
+ return 1;
+}