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| author | Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> | 2020-12-03 14:07:15 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-12-14 23:05:25 +0000 |
| commit | 87c7ec7c0677ec5fda4a9cebb95c06edb23a96ba (patch) | |
| tree | 0851933ccc52497f866c0aebaff15871db8375c6 /src/soc/qualcomm/qcs405/blsp.c | |
| parent | 5f7343273708490137163445c4a3ba38ed2b7b1e (diff) | |
soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config option
SF Mask MSRs' Programming which was done under this config
selection will be moved under a new config option called
CAR_HAS_SF_MASKS. This segregates the eNEM programming
sequence based on sub features supported in each processor.
Bug=b:171601324
BRANCH=volteer
Test=Build volteer build and boot on Delbin EVT.
Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/qualcomm/qcs405/blsp.c')
0 files changed, 0 insertions, 0 deletions