qcs405: clock: Adding the clock support for qcs405

Add basic clock support and enable UART, SPI clocks.

Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Signed-off-by: Pranav Agrawal <pranava@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc
index c702264739..89a7354557 100644
--- a/src/soc/qualcomm/qcs405/Makefile.inc
+++ b/src/soc/qualcomm/qcs405/Makefile.inc
@@ -7,17 +7,20 @@ bootblock-y += timer.c
 bootblock-y += spi.c
 bootblock-y += mmu.c
 bootblock-y += gpio.c
+bootblock-y += clock.c
 
 ################################################################################
 verstage-y += timer.c
 verstage-y += spi.c
 verstage-y += gpio.c
+verstage-y += clock.c
 
 ################################################################################
 romstage-y += timer.c
 romstage-y += spi.c
 romstage-y += cbmem.c
 romstage-y += gpio.c
+romstage-y += clock.c
 
 ################################################################################
 ramstage-y += soc.c
@@ -25,6 +28,7 @@ ramstage-y += timer.c
 ramstage-y += spi.c
 ramstage-y += cbmem.c
 ramstage-y += gpio.c
+ramstage-y += clock.c
 
 ################################################################################