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authorHarsha B R <harsha.b.r@intel.com>2023-02-01 13:20:35 +0530
committerSridhar Siricilla <sridhar.siricilla@intel.com>2023-02-07 07:17:14 +0000
commita891f71ad54898712e3f4228afcd05169cebb784 (patch)
treef3a548bdc8b5b00f7de53a0653605387d61a1447 /src/soc/qualcomm/ipq806x
parent453805ceb948b1a8de545c4547b38bb45b5206ed (diff)
mb/intel/mtlrvp: Enable GSPI interface
This patch enables GSPI [1] interface for mtlrvp based on mtlrvp schematics. BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to ChromeOS. (Base patch for CB:71223) SPI[0].Mode = 0 SPI[0].DefaultCsOutput = 0 SPI[0].CsMode = 0 SPI[0].CsState = 0 SPI[1].Mode = 1 SPI[1].DefaultCsOutput = 0 SPI[1].CsMode = 0 SPI[1].CsState = 0 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/soc/qualcomm/ipq806x')
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