diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/qualcomm/ipq806x/usb.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/usb.c')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/usb.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index 35285cd0d5..003bc7bf0b 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -127,9 +127,9 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) udelay(5); - clrbits_le32(&dwc3->ctl, 0x1 << 11); /* deassert core soft reset */ - clrbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ - clrbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ + clrbits32(&dwc3->ctl, 0x1 << 11); /* deassert core soft reset */ + clrbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ + clrbits32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ } static void setup_phy(struct usb_qc_phy *phy) @@ -164,7 +164,7 @@ static void setup_phy(struct usb_qc_phy *phy) write32(&phy->general_cfg, 0x1 << 2); /* set XHCI 1.00 compliance */ udelay(5); - clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */ + clrbits32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */ } static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data) @@ -206,7 +206,7 @@ static void tune_phy(struct usb_qc_phy *phy) void setup_usb_host1(void) { printk(BIOS_INFO, "Setting up USB HOST1 controller...\n"); - setbits_le32(tcsr_usb_sel, 1 << 0); /* Select DWC3 controller */ + setbits32(tcsr_usb_sel, 1 << 0); /* Select DWC3 controller */ setup_phy(usb_host1_phy); setup_dwc3(usb_host1_dwc3); tune_phy(usb_host1_phy); @@ -215,7 +215,7 @@ void setup_usb_host1(void) void setup_usb_host2(void) { printk(BIOS_INFO, "Setting up USB HOST2 controller...\n"); - setbits_le32(tcsr_usb_sel, 1 << 1); /* Select DWC3 controller */ + setbits32(tcsr_usb_sel, 1 << 1); /* Select DWC3 controller */ setup_phy(usb_host2_phy); setup_dwc3(usb_host2_dwc3); tune_phy(usb_host2_phy); |