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authorAaron Durbin <adurbin@chromium.org>2014-07-21 22:11:29 -0500
committerMarc Jones <marc.jones@se-eng.com>2015-03-13 00:17:09 +0100
commit44f465d21cad78c87c32b916f72e1bff2ef532a0 (patch)
tree680ea7fe809c7994d3db75c12bb35dad21966b90 /src/soc/qualcomm/ipq806x/usb.c
parent7ddb5f76feea37ed055f2eede944c2971214e2f2 (diff)
tegra132: fix Rx FIFO underruns with slower SPI clock
The SPI controller operates on packets which can be variable length up to 32-bit packets. It also has the ability to be put in packed or unpacked mode w.r.t each packet. i.e. does a single fifo register hold >= 1 packet. The current programming uses 8-bit packets in unpacked mode which means 4 fifo slots are used for a 32-bit DMA transfter. As the AHB can only operate on a minimum of 32-bit bursts the triggers need to be programmed correctly so that there is room for a full 32-bit DMA transaction. Previously faster SPI clocks just made things magically work. BUG=chrome-os-partner:30779 BRANCH=None TEST=Built and booted through coreboot with 20MHz SPI clock. Original-Change-Id: I3f1cd4dddcea9514327b2363ed450a527db7e1fe Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208862 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit d9864228a2479e412d7e0d2221fe536f78329acd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I61c145f35e1f889d4f83f3dfea049bfd347c1196 Reviewed-on: http://review.coreboot.org/8649 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/usb.c')
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