diff options
| author | David Hendricks <dhendrix@chromium.org> | 2014-07-02 13:50:57 -0700 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-01-09 06:21:08 +0100 |
| commit | 24452743472a2480b88465de22db8adc7a9b544c (patch) | |
| tree | f91160cb31b8d2498d8c7506688d71f4053fe46e /src/soc/qualcomm/ipq806x/soc.c | |
| parent | 0c0767c238210d7bb5e504e985ad44679f7eb6da (diff) | |
storm: Reserve memory from 0x4000_0000-0x414f_ffff
This marks the bottom chunk of memory, which is used by various IP
blocks, as reserved so that Depthcharge does not attempt to wipe it.
BUG=chrome-os-partner:30067
BRANCH=storm
TEST=Built and booted for storm, depthcharge shows:
Wipe memory regions:
[0x00000041500000, 0x00000051000000)
[0x000000510006a0, 0x00000053000000)
[0x00000054141260, 0x0000007fffd000)
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I8f782f16d13620b705e1b3fbeca21dc8705b7e77
Original-Reviewed-on: https://chromium-review.googlesource.com/206516
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit f66f553f1594c481a74b7f40b4b1088600b1a70a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I82d118abc86052f5e32f6195a4efd04fe315be5a
Reviewed-on: http://review.coreboot.org/8149
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/soc.c')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/soc.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/soc/qualcomm/ipq806x/soc.c b/src/soc/qualcomm/ipq806x/soc.c index 53f5716c07..6421ccdadd 100644 --- a/src/soc/qualcomm/ipq806x/soc.c +++ b/src/soc/qualcomm/ipq806x/soc.c @@ -22,10 +22,16 @@ #include <console/console.h> #include <device/device.h> + +#define RESERVED_SIZE_KB (0x01500000 / KiB) + static void soc_read_resources(device_t dev) { - ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, - CONFIG_DRAM_SIZE_MB * (1 << 10)); + /* Reserve bottom 0x150_0000 bytes for NSS, SMEM, etc. */ + reserved_ram_resource(dev, 0, + CONFIG_SYS_SDRAM_BASE/KiB, RESERVED_SIZE_KB); + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB + RESERVED_SIZE_KB, + (CONFIG_DRAM_SIZE_MB * KiB) - RESERVED_SIZE_KB); } static void soc_init(device_t dev) |