diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-28 16:26:43 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 09:20:52 +0000 |
| commit | 05498a254d5364efb669f63aa4b042c91c123727 (patch) | |
| tree | 21fe95cd426c1da7a2ea54f44bfcb1566731308d /src/soc/qualcomm/ipq806x/include | |
| parent | e7f4beca19d538c47208b8a1b984cf0e39ff02b4 (diff) | |
src/soc: Get rid of whitespace before tab
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/include')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/soc/iomap.h | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h index 4a3aa49140..18751a8753 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h @@ -101,12 +101,12 @@ #define USB_HOST1_PHY_BASE 0x110F8800 #define GSBI_4 4 -#define UART1_DM_BASE 0x12450000 -#define UART_GSBI1_BASE 0x12440000 +#define UART1_DM_BASE 0x12450000 +#define UART_GSBI1_BASE 0x12440000 #define UART2_DM_BASE 0x12490000 #define UART_GSBI2_BASE 0x12480000 -#define UART4_DM_BASE 0x16340000 -#define UART_GSBI4_BASE 0x16300000 +#define UART4_DM_BASE 0x16340000 +#define UART_GSBI4_BASE 0x16300000 #define UART2_DM_BASE 0x12490000 #define UART_GSBI2_BASE 0x12480000 @@ -135,25 +135,25 @@ #define GSBI_QUP6_BASE (GSBI6_BASE + 0x80000) #define GSBI_QUP7_BASE (GSBI7_BASE + 0x80000) -#define GSBI_CTL_PROTO_I2C 2 -#define GSBI_CTL_PROTO_CODE_SFT 4 -#define GSBI_CTL_PROTO_CODE_MSK 0x7 -#define GSBI_HCLK_CTL_GATE_ENA 6 -#define GSBI_HCLK_CTL_BRANCH_ENA 4 -#define GSBI_QUP_APPS_M_SHFT 16 -#define GSBI_QUP_APPS_M_MASK 0xFF -#define GSBI_QUP_APPS_D_SHFT 0 -#define GSBI_QUP_APPS_D_MASK 0xFF -#define GSBI_QUP_APPS_N_SHFT 16 -#define GSBI_QUP_APPS_N_MASK 0xFF -#define GSBI_QUP_APPS_ROOT_ENA_SFT 11 -#define GSBI_QUP_APPS_BRANCH_ENA_SFT 9 -#define GSBI_QUP_APPS_MNCTR_EN_SFT 8 -#define GSBI_QUP_APPS_MNCTR_MODE_MSK 0x3 -#define GSBI_QUP_APPS_MNCTR_MODE_SFT 5 -#define GSBI_QUP_APPS_PRE_DIV_MSK 0x3 -#define GSBI_QUP_APPS_PRE_DIV_SFT 3 -#define GSBI_QUP_APPS_SRC_SEL_MSK 0x7 +#define GSBI_CTL_PROTO_I2C 2 +#define GSBI_CTL_PROTO_CODE_SFT 4 +#define GSBI_CTL_PROTO_CODE_MSK 0x7 +#define GSBI_HCLK_CTL_GATE_ENA 6 +#define GSBI_HCLK_CTL_BRANCH_ENA 4 +#define GSBI_QUP_APPS_M_SHFT 16 +#define GSBI_QUP_APPS_M_MASK 0xFF +#define GSBI_QUP_APPS_D_SHFT 0 +#define GSBI_QUP_APPS_D_MASK 0xFF +#define GSBI_QUP_APPS_N_SHFT 16 +#define GSBI_QUP_APPS_N_MASK 0xFF +#define GSBI_QUP_APPS_ROOT_ENA_SFT 11 +#define GSBI_QUP_APPS_BRANCH_ENA_SFT 9 +#define GSBI_QUP_APPS_MNCTR_EN_SFT 8 +#define GSBI_QUP_APPS_MNCTR_MODE_MSK 0x3 +#define GSBI_QUP_APPS_MNCTR_MODE_SFT 5 +#define GSBI_QUP_APPS_PRE_DIV_MSK 0x3 +#define GSBI_QUP_APPS_PRE_DIV_SFT 3 +#define GSBI_QUP_APPS_SRC_SEL_MSK 0x7 #define GSBI_QUP_APSS_MD_REG(gsbi_n) ((MSM_CLK_CTL_BASE + 0x29c8) + \ |