diff options
author | Vadim Bendebury <vbendeb@chromium.org> | 2014-04-23 13:42:22 -0700 |
---|---|---|
committer | Marc Jones <marc.jones@se-eng.com> | 2014-12-30 20:17:39 +0100 |
commit | 4f062ae381db3c7e5b1b64ce22db374f63f048d7 (patch) | |
tree | c19003460ee720272ea702a1c047376dd1366604 /src/soc/qualcomm/ipq806x/include/gsbi.h | |
parent | 6a3f92f55c7288e1b8cde00088188bcd9171139e (diff) |
ipq8064: prepare include files before adding UART driver
These patch modifies .h files to match the coreboot API. A few more
significant changes are:
- UART specific fields removed from common board structure in cdp.h.
These fields are set at compile time in u-boot (where this
structure comes from), they will be set in a different structure in
the UART driver in an upcoming patch.
- an inline wrapper is added in gpio.h to provide GPIO API the UART
driver expects.
- the ipq_configure_gpio() is passed the descriptor placed in ro data.
BUG=chrome-os-partner:27784
TEST=none
Original-Change-Id: Id49507fb0c72ef993a89b538cd417b6c86ae3786
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196661
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit ea400f1b720eb671fa411c5fd1df7efd14fdacd6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2c7be09675b225de99be3c94b22e9ee2ebb2cb9a
Reviewed-on: http://review.coreboot.org/7873
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/include/gsbi.h')
-rw-r--r-- | src/soc/qualcomm/ipq806x/include/gsbi.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/qualcomm/ipq806x/include/gsbi.h b/src/soc/qualcomm/ipq806x/include/gsbi.h index d2ba2b310a..c12d6fd7b4 100644 --- a/src/soc/qualcomm/ipq806x/include/gsbi.h +++ b/src/soc/qualcomm/ipq806x/include/gsbi.h @@ -19,8 +19,6 @@ #ifndef __GSBI_H_ #define __GSBI_H_ -#include <asm/io.h> - /* GSBI Registers */ #define GSBI_CTRL_REG(base) ((base) + 0x0) |