diff options
| author | Julius Werner <jwerner@chromium.org> | 2014-05-30 18:01:44 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-04 00:15:17 +0100 |
| commit | 028cba9266e531d9d7c5e39432bbb7eeda6398ed (patch) | |
| tree | 20e7c32ea7fb9c1d676790a2b8f20f7a0bf45f03 /src/soc/qualcomm/ipq806x/include/clock.h | |
| parent | 96ef1883a7a8b95f297f99fa7409f27c0f344d88 (diff) | |
ipq806x: Add USB support
This patch adds code to initialize the two DWC3 USB host controllers and
their associated PHYs to the IPQ806x SoC (closely imitating the existing
DWC3 implementation for Exynos5), and uses them to initialize USB on the
Storm mainboard.
BUG=chrome-os-partner:29375
TEST=Hack up netboot to get around missing SPI flash, load a file over
TFTP. Hack a storage read into the storage attach function, dump the
data and confirm that it looks right. Enable USB debugging and confirm
3.0 devices get enumerated at SuperSpeed (mostly).
Original-Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202157
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 6349e7281d5accb1247acb0537a48fa3a5e1bf97)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I749d265d45c6a807a7559bd4df2490a6eb8067af
Reviewed-on: http://review.coreboot.org/8056
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/include/clock.h')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/clock.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq806x/include/clock.h b/src/soc/qualcomm/ipq806x/include/clock.h index c5d4121169..98f6661e02 100644 --- a/src/soc/qualcomm/ipq806x/include/clock.h +++ b/src/soc/qualcomm/ipq806x/include/clock.h @@ -63,6 +63,16 @@ #define CFPB_SPLITTER_HCLK_CTL_REG REG(0x026E0) #define EBI2_CLK_CTL_REG REG(0x03B00) +#define USB30_MASTER_CLK_CTL_REG REG(0x3b24) +#define USB30_MASTER_CLK_MD REG(0x3b28) +#define USB30_MASTER_CLK_NS REG(0x3b2c) +#define USB30_1_MASTER_CLK_CTL_REG REG(0x3b34) +#define USB30_MOC_UTMI_CLK_MD REG(0x3b40) +#define USB30_MOC_UTMI_CLK_NS REG(0x3b44) +#define USB30_MOC_UTMI_CLK_CTL REG(0x3b48) +#define USB30_1_MOC_UTMI_CLK_CTL REG(0x3b4c) +#define USB30_RESET REG(0x3b50) + #define ALWAYS_ON_CLK_BRANCH_ENA(i) ((i) << 8) #define CLK_BRANCH_ENA_MASK 0x00000010 @@ -182,5 +192,6 @@ void uart_pll_vote_clk_enable(unsigned int); void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n, unsigned int d, unsigned int clk_dummy); void nand_clock_config(void); +void usb_clock_config(void); #endif /* __PLATFORM_IPQ860X_CLOCK_H_ */ |