diff options
| author | Julius Werner <jwerner@chromium.org> | 2015-02-19 14:51:15 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:22:28 +0200 |
| commit | 2f37bd65518865688b9234afce0d467508d6f465 (patch) | |
| tree | eba5ed799de966299602b30c70d51dd40eaadd73 /src/soc/qualcomm/ipq806x/gsbi.c | |
| parent | 1f60f971fc89ef841e81b978964b38278d597b1d (diff) | |
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/:
@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/gsbi.c')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/gsbi.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/qualcomm/ipq806x/gsbi.c b/src/soc/qualcomm/ipq806x/gsbi.c index 54adbe8db7..93270958a9 100644 --- a/src/soc/qualcomm/ipq806x/gsbi.c +++ b/src/soc/qualcomm/ipq806x/gsbi.c @@ -68,18 +68,18 @@ gsbi_return_t gsbi_init(gsbi_id_t gsbi_id, gsbi_protocol_t protocol) if (!gsbi_ctl) return GSBI_ID_ERROR; - writel((1 << GSBI_HCLK_CTL_GATE_ENA) | (1 << GSBI_HCLK_CTL_BRANCH_ENA), - GSBI_HCLK_CTL(gsbi_id)); + write32(GSBI_HCLK_CTL(gsbi_id), + (1 << GSBI_HCLK_CTL_GATE_ENA) | (1 << GSBI_HCLK_CTL_BRANCH_ENA)); if (gsbi_init_board(gsbi_id)) return GSBI_UNSUPPORTED; - writel(0, GSBI_QUP_APSS_NS_REG(gsbi_id)); - writel(0, GSBI_QUP_APSS_MD_REG(gsbi_id)); + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), 0); + write32(GSBI_QUP_APSS_MD_REG(gsbi_id), 0); reg_val = ((m & GSBI_QUP_APPS_M_MASK) << GSBI_QUP_APPS_M_SHFT) | ((~n & GSBI_QUP_APPS_D_MASK) << GSBI_QUP_APPS_D_SHFT); - writel(reg_val, GSBI_QUP_APSS_MD_REG(gsbi_id)); + write32(GSBI_QUP_APSS_MD_REG(gsbi_id), reg_val); reg_val = (((~(n - m)) & GSBI_QUP_APPS_N_MASK) << GSBI_QUP_APPS_N_SHFT) | @@ -88,18 +88,18 @@ gsbi_return_t gsbi_init(gsbi_id_t gsbi_id, gsbi_protocol_t protocol) (((pre_div - 1) & GSBI_QUP_APPS_PRE_DIV_MSK) << GSBI_QUP_APPS_PRE_DIV_SFT) | (src & GSBI_QUP_APPS_SRC_SEL_MSK); - writel(reg_val, GSBI_QUP_APSS_NS_REG(gsbi_id)); + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val); reg_val |= (1 << GSBI_QUP_APPS_ROOT_ENA_SFT) | (1 << GSBI_QUP_APPS_MNCTR_EN_SFT); - writel(reg_val, GSBI_QUP_APSS_NS_REG(gsbi_id)); + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val); reg_val |= (1 << GSBI_QUP_APPS_BRANCH_ENA_SFT); - writel(reg_val, GSBI_QUP_APSS_NS_REG(gsbi_id)); + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val); /*Select i2c protocol*/ - writel(((GSBI_CTL_PROTO_I2C & GSBI_CTL_PROTO_CODE_MSK) << - GSBI_CTL_PROTO_CODE_SFT), gsbi_ctl); + write32(gsbi_ctl, + ((GSBI_CTL_PROTO_I2C & GSBI_CTL_PROTO_CODE_MSK) << GSBI_CTL_PROTO_CODE_SFT)); return GSBI_SUCCESS; } |