arm(64): Replace write32() and friends with writel()

This patch is a raw application of the following spatch to the
directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>,
src/soc/<arm(64)-soc> and src/drivers/gic:

@@
expression A, V;
@@
- write32(V, A)
+ writel(V, A)
@@
expression A, V;
@@
- write16(V, A)
+ writew(V, A)
@@
expression A, V;
@@
- write8(V, A)
+ writeb(V, A)

This replaces all uses of write{32,16,8}() with write{l,w,b}()
which is currently equivalent and much more common. This is a
preparatory step that will allow us to easier flip them all at once to
the new write32(a,v) model.

BRANCH=none
BUG=chromium:451388
TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky.

Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24
Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254862
Reviewed-on: http://review.coreboot.org/9834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 12 insertions, 17 deletions

diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c
index fe7cfb83a8..0b770da94f 100644
--- a/src/soc/qualcomm/ipq806x/clock.c
+++ b/src/soc/qualcomm/ipq806x/clock.c
@@ -126,22 +126,17 @@ void nand_clock_config(void)
 void usb_clock_config(void)
 {
 	/* Magic clock initialization numbers, nobody knows how they work... */
-	write32(0x10, USB30_MASTER_CLK_CTL_REG);
-	write32(0x10, USB30_1_MASTER_CLK_CTL_REG);
-	write32(0x500DF, USB30_MASTER_CLK_MD);
-	write32(0xE40942, USB30_MASTER_CLK_NS);
-	write32(0x100D7, USB30_MOC_UTMI_CLK_MD);
-	write32(0xD80942, USB30_MOC_UTMI_CLK_NS);
-	write32(0x10, USB30_MOC_UTMI_CLK_CTL);
-	write32(0x10, USB30_1_MOC_UTMI_CLK_CTL);
-
-	write32(1 << 5 |		/* assert port2 HS PHY async reset */
-		1 << 4 |		/* assert master async reset */
-		1 << 3 |		/* assert sleep async reset */
-		1 << 2 |		/* assert MOC UTMI async reset */
-		1 << 1 |		/* assert power-on async reset */
-		1 << 0 |		/* assert PHY async reset */
-		0, USB30_RESET);
+	writel(0x10, USB30_MASTER_CLK_CTL_REG);
+	writel(0x10, USB30_1_MASTER_CLK_CTL_REG);
+	writel(0x500DF, USB30_MASTER_CLK_MD);
+	writel(0xE40942, USB30_MASTER_CLK_NS);
+	writel(0x100D7, USB30_MOC_UTMI_CLK_MD);
+	writel(0xD80942, USB30_MOC_UTMI_CLK_NS);
+	writel(0x10, USB30_MOC_UTMI_CLK_CTL);
+	writel(0x10, USB30_1_MOC_UTMI_CLK_CTL);
+
+	writel(1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0 | 0,
+	       USB30_RESET);
 	udelay(5);
-	write32(0, USB30_RESET);	/* deassert all USB resets again */
+	writel(0, USB30_RESET);	/* deassert all USB resets again */
 }