diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/qualcomm/ipq806x/clock.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/clock.c')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/clock.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 15ea852ae8..5b7469c3fb 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -23,7 +23,7 @@ */ void uart_pll_vote_clk_enable(unsigned int clk_dummy) { - setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8)); + setbits32(BB_PLL_ENA_SC0_REG, BIT(8)); if (!clk_dummy) while ((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0); @@ -39,11 +39,11 @@ static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m, unsigned int n) { /* Assert MND reset. */ - setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); + setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); /* Program M and D values. */ write32(GSBIn_UART_APPS_MD_REG(gsbi_port), MD16(m, n)); /* Deassert MND reset. */ - clrbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); + clrbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); } /** @@ -53,7 +53,7 @@ static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m, */ static void uart_branch_clk_enable_reg(unsigned int gsbi_port) { - setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9)); + setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9)); } /** @@ -100,7 +100,7 @@ static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n, */ static void uart_set_gsbi_clk(unsigned int gsbi_port) { - setbits_le32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4)); + setbits32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4)); } /** |