diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-17 17:02:53 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-22 21:22:44 +0000 |
| commit | d972f78e759ffccf9187ab3f3b00b567c7f30f53 (patch) | |
| tree | 435ba6384408f63a21c633141a9d1bece8079421 /src/soc/qualcomm/ipq806x/Makefile.inc | |
| parent | f66a026d70961832164ca4edd701d762384786b3 (diff) | |
linking: link bootblock.elf with .data and .bss sections again
Currently coreboot expects the loader to clear the bss section
for all stages. i.e. stages don't clear their own bss. On ARM
SoCs the BootROM would be responsible for this. To do that
one needs to include the bss section data (all zeros) in the
bootblock.bin file. This was previously being attempted by
keeping the .bss info in the .data section because objcopy
happened zero out non-file allocated data section data.
Instead go back to linking bootblock with the bss section
but mark the bss section as loadable allocatable data. That
way it will be included in the binary properly when objcopy
-O binary is emplyed. Also do the same for the data section
in the case of no non-zero object values are in the data
section.
Without this change the trick of including .bss in .data
was not working when there wasn't a non-zero value object
in the data section.
BUG=None
BRANCH=None
TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
the cleared bss.
Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/Makefile.inc')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/Makefile.inc | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 84eae0be51..83b5e060c8 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -56,14 +56,8 @@ ramstage-y += tz_wrapper.S ifeq ($(CONFIG_USE_BLOBS),y) -# Generate the actual coreboot bootblock code -$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - $(OBJCOPY_bootblock) -O binary $< $@.tmp - @mv $@.tmp $@ - # Add MBN header to allow SBL3 to start coreboot bootblock -$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw +$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin @printf " ADD MBN $(subst $(obj)/,,$(@))\n" ./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp @mv $@.tmp $@ |