storm: ipq8064: enable CBFS SPI wrapper

This change forces storm platform to use the common CBFS SPI wrapper,
which makes the SOC specific CBFS code unnecessary and requires
including SPI controller support in all coreboot stages.

BUG=chrome-os-partner:27784
TEST=manual
  . with this change and the rest of the patches coreboot on AP148
    comes up all the way to attempting to boot the payload (reading
    earlier stages from the SPI flash along the way).

Original-Change-Id: Ib468096f8e844deca11909293d90fc327aa99787
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197932
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 794418a132b5be5a2c049f28202da3cec7ce478d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I751c51c91f29da4f54fcfe05e7b9a2e8f956c4f2
Reviewed-on: http://review.coreboot.org/7994
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 639b9d9f45..94c7cb9089 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -18,21 +18,21 @@
 ##
 
 bootblock-y += bootblock.c
-bootblock-y += cbfs.c
 bootblock-y += clock.c
 bootblock-y += gpio.c
+bootblock-$(CONFIG_SPI_FLASH) += spi.c
 bootblock-y += timer.c
 bootblock-$(CONFIG_DRIVERS_UART) += uart.c
 
-romstage-y += cbfs.c
 romstage-y += clock.c
 romstage-y += gpio.c
+romstage-$(CONFIG_SPI_FLASH) += spi.c
 romstage-y += timer.c
 romstage-$(CONFIG_DRIVERS_UART) += uart.c
 
-ramstage-y += cbfs.c
 ramstage-y += clock.c
 ramstage-y += gpio.c
+ramstage-$(CONFIG_SPI_FLASH) += spi.c
 ramstage-y += timer.c
 ramstage-$(CONFIG_DRIVERS_UART) += uart.c