diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-10-02 17:28:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-12-02 22:12:10 +0000 |
| commit | baf27dbaeb1f6791ebfc416f2175507686bd88ac (patch) | |
| tree | 55c9d8224cde44d732b183624abf76b7446e418e /src/soc/qualcomm/ipq40xx | |
| parent | 4a1cbdd51aafa671ecb6c93a475ca9bf6f9ca914 (diff) | |
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/qualcomm/ipq40xx')
| -rw-r--r-- | src/soc/qualcomm/ipq40xx/memlayout.ld | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/qualcomm/ipq40xx/memlayout.ld b/src/soc/qualcomm/ipq40xx/memlayout.ld index 1a2dd31cc4..4c542949cd 100644 --- a/src/soc/qualcomm/ipq40xx/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/memlayout.ld @@ -20,7 +20,8 @@ SECTIONS /* This includes bootblock image, can be reused after bootblock starts */ /* UBER_SBL(0x0A0C0000, 48K) */ - PRERAM_CBFS_CACHE(0x0A0C0000, 92K) + PRERAM_CBFS_CACHE(0x0A0C0000, 84K) + CBFS_MCACHE(0x0A0ED800, 8K) FMAP_CACHE(0x0A0EF800, 2K) TTB(0x0A0F0000, 16K) |