diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-27 07:13:55 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-14 20:58:43 +0000 |
| commit | d3c58fdc6436b2c4455b07fe764fcae471a65433 (patch) | |
| tree | ba640e7839435bea341bf796a2e63921594a72de /src/soc/qualcomm/ipq40xx | |
| parent | 211792feaba4a5cc26b4e3f17e905c3e899eb07f (diff) | |
soc/qualcomm: Link cbmem.c only in romstage
Change-Id: I008fcca024fecf462c4b550b8dedbf4b06e491b8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36368
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq40xx')
| -rw-r--r-- | src/soc/qualcomm/ipq40xx/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq40xx/cbmem.c | 2 |
2 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index 6447acf1d6..b20ae24d60 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -16,7 +16,6 @@ ifeq ($(CONFIG_SOC_QC_IPQ40XX),y) bootblock-y += clock.c -bootblock-y += cbmem.c bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += timer.c @@ -43,7 +42,6 @@ romstage-y += blsp.c romstage-y += qup.c ramstage-y += blobs_init.c -ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += lcc.c diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 972c6258c9..9970758d91 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -31,7 +31,7 @@ void *cbmem_top_chipset(void) * with components that utilize cbmem in romstage (e.g. vboot_locator * for loading ipq blobs before DRAM is initialized). */ - if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + if (cbmem_backing_store_ready == 0) return NULL; return _memlayout_cbmem_top; |