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authorReka Norman <rekanorman@google.com>2022-11-14 11:55:09 +1100
committerFelix Held <felix-coreboot@felixheld.de>2022-11-15 16:25:18 +0000
commit5013f7d152578cc7301242161cba7650a78eb4c1 (patch)
tree89ac85f90a5a93d1a004c06d67923a3c4abd8b15 /src/soc/qualcomm/ipq40xx/soc.c
parentcf92ecf6f149730d18d308a8c9c67a8785a0d850 (diff)
mb/google/nissa: Remove SI_ME subregions
The SI_ME subregions were added to support using the CSE stitching tools (cse_serger). Use of the stitching tools has been reverted and probably won't be re-enabled soon, so the subregions are not currently used by anything. They also don't match the actual region sizes chosen by the FIT tool, so remove them to avoid confusion. The other option would be to manually keep them in sync with the sizes chosen by the FIT tool, but this would be extra manual effort without much benefit. BUG=None TEST=Build and boot on nivviks Change-Id: I993e07a060445ab8de1b0e40a023e8248867c53c Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69540 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/soc/qualcomm/ipq40xx/soc.c')
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