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authorFurquan Shaikh <furquan@google.com>2020-06-11 11:59:07 -0700
committerFurquan Shaikh <furquan@google.com>2020-06-13 06:49:23 +0000
commit46514c2b877c29c2d7c2061a9785736e270c0c62 (patch)
tree2f78550192bce548139ef49fdac6623dad578703 /src/soc/qualcomm/ipq40xx/memlayout.ld
parent00148bba7146318e2e815d8c13e33278f63814c9 (diff)
treewide: Add Kconfig variable MEMLAYOUT_LD_FILE
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq40xx/memlayout.ld')
-rw-r--r--src/soc/qualcomm/ipq40xx/memlayout.ld51
1 files changed, 51 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq40xx/memlayout.ld b/src/soc/qualcomm/ipq40xx/memlayout.ld
new file mode 100644
index 0000000000..1a2dd31cc4
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/memlayout.ld
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+#define REGION_START(name, addr) SYMBOL(name, addr)
+#define REGION_END(name, addr) SYMBOL(e##name, addr)
+
+SECTIONS
+{
+ REGION(oc_imem, 0x08600000, 32K, 0)
+
+ /* ==vvv== OC_IMEM_1_START 0x08600000 ==vvv== */
+/* DDR(0x08600000, 32K) */
+ /* ==^^^== OC_IMEM_1_END 0x08608000 ==^^^== */
+
+ /* ==vvv== WIFI_IMEM_0_START 0x0A0C0000 ==vvv== */
+ REGION_START(wifi_imem_0, 0x0A0C0000)
+ /* This includes bootblock image, can be reused after bootblock starts */
+/* UBER_SBL(0x0A0C0000, 48K) */
+
+ PRERAM_CBFS_CACHE(0x0A0C0000, 92K)
+ FMAP_CACHE(0x0A0EF800, 2K)
+
+ TTB(0x0A0F0000, 16K)
+ TTB_SUBTABLES(0x0A0F4000, 4K)
+ REGION_END(wifi_imem_0, 0x0A100000)
+ /* ==^^^== WIFI_IMEM_0_END 0x0A100000 ==^^^== */
+
+
+ /* ==vvv== WIFI_IMEM_1_START 0x0A8C0000 ==vvv== */
+ REGION_START(wifi_imem_1, 0x0A8C0000)
+ BOOTBLOCK(0x0A8C0000, 24K)
+ OVERLAP_VERSTAGE_ROMSTAGE(0x0A8C6000, 64K)
+ VBOOT2_WORK(0x0A8D6000, 12K)
+ PRERAM_CBMEM_CONSOLE(0x0A8DA000, 32K)
+ TIMESTAMP(0x0A8E2000, 1K)
+
+/* 0x0A8E2400..0x0A8FC000 103 KB free */
+
+ STACK(0x0A8FC000, 16K)
+ REGION_END(wifi_imem_1, 0x0A900000)
+ /* ==^^^== WIFI_IMEM_1_END 0x0A900000 ==^^^== */
+
+ DRAM_START(0x80000000)
+ SYMBOL(memlayout_cbmem_top, 0x87280000)
+ POSTRAM_CBFS_CACHE(0x87280000, 512K)
+ RAMSTAGE(0x87300000, 512K)
+ DMA_COHERENT(0x87400000, 2M)
+}