diff options
| author | Kan Yan <kyan@google.com> | 2018-10-22 14:10:43 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-08-30 10:43:42 +0000 |
| commit | eefb5900d0b374019c0070846f55f9b5bedac7ad (patch) | |
| tree | 2883210bdb1f69c562caa2a318610c9835d89adf /src/soc/qualcomm/ipq40xx/include | |
| parent | 7b2deddbb0ef350e189fe42c025b07c943aedc4c (diff) | |
ipq40xx: Increase CBFS and RAMSTAGE size
Increase CBFS and RAMSTAGE size to accommodate larger binary component.
BUG=b:77641795
TEST=Build and test on Gale.
BRANCH=none
Change-Id: I25f7121221ab2bb66dfedbc4a66e06976d88cef5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e4d3d2d078d0a8f705afe2b6c741118727614bf0
Original-Change-Id: I6ad16c0073a683cb66d5ae8a46b8990f3346f183
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1366388
Original-Reviewed-by: Zhihong Yu <zhihongyu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35134
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq40xx/include')
| -rw-r--r-- | src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index a69b60bfb9..f1a7bc59d2 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -58,7 +58,7 @@ SECTIONS DRAM_START(0x80000000) SYMBOL(memlayout_cbmem_top, 0x87280000) - POSTRAM_CBFS_CACHE(0x87280000, 384K) - RAMSTAGE(0x872e0000, 128K) - DMA_COHERENT(0x87300000, 2M) + POSTRAM_CBFS_CACHE(0x87280000, 512K) + RAMSTAGE(0x87300000, 512K) + DMA_COHERENT(0x87400000, 2M) } |