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authorVaradarajan Narayanan <varada@codeaurora.org>2016-03-02 16:57:10 +0530
committerPatrick Georgi <pgeorgi@google.com>2016-05-10 21:34:21 +0200
commita6935c2508c426f30d6bf5bcf4c3130277a0f998 (patch)
treee844bb803e8c069101fdf6ec47017af9dc832713 /src/soc/qualcomm/ipq40xx/include
parentc84e2fe893e02de3c5d97d26d05462351ac90d91 (diff)
soc/qualcomm/ipq40xx: Initial commit for IPQ40xx SoC support
Copy 'ipq806x' files as a template BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: dc6a5937953fe61cd4b5a99ca49f9371c4b712d4 Original-Change-Id: If171fcdd3b0561cb6b7dab5f8434de7ef711ea41 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/333178 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Update ipq806x/storm references Since the files were taken from ipq806x/storm as template. Update those references to reflect ipq40xx/gale. BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: c6c76d184cc92c09e6826fbdc7d7fac59b2cb69b Original-Change-Id: Ieae1bce25291243b4a6034d37a6949978f318997 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333293 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ie5794c48131ae562861074b406106734541880d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14644 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/qualcomm/ipq40xx/include')
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/cdp.h177
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/clock.h214
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/ebi2.h107
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/gpio.h110
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/gsbi.h75
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/iomap.h165
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/ipq_timer.h37
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h273
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/lcc-reg.h341
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld51
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/qup.h219
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/soc_services.h35
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/spi.h305
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/usb.h22
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h70
15 files changed, 2201 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h
new file mode 100644
index 0000000000..57c679e12e
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2012 The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _IPQ40XX_CDP_H_
+#define _IPQ40XX_CDP_H_
+
+#include <types.h>
+
+unsigned smem_get_board_machtype(void);
+
+typedef enum {
+ PHY_INTERFACE_MODE_MII,
+ PHY_INTERFACE_MODE_GMII,
+ PHY_INTERFACE_MODE_SGMII,
+ PHY_INTERFACE_MODE_QSGMII,
+ PHY_INTERFACE_MODE_TBI,
+ PHY_INTERFACE_MODE_RMII,
+ PHY_INTERFACE_MODE_RGMII,
+ PHY_INTERFACE_MODE_RGMII_ID,
+ PHY_INTERFACE_MODE_RGMII_RXID,
+ PHY_INTERFACE_MODE_RGMII_TXID,
+ PHY_INTERFACE_MODE_RTBI,
+ PHY_INTERFACE_MODE_XGMII,
+ PHY_INTERFACE_MODE_NONE /* Must be last */
+} phy_interface_t;
+
+typedef struct {
+ unsigned int gpio;
+ unsigned int func;
+ unsigned int dir;
+ unsigned int pull;
+ unsigned int drvstr;
+ unsigned int enable;
+} gpio_func_data_t;
+
+typedef struct {
+ unsigned int m_value;
+ unsigned int n_value;
+ unsigned int d_value;
+} uart_clk_mnd_t;
+
+/* SPI Mode */
+
+typedef enum {
+ NOR_SPI_MODE_0,
+ NOR_SPI_MODE_1,
+ NOR_SPI_MODE_2,
+ NOR_SPI_MODE_3,
+} spi_mode;
+
+/* SPI GSBI Bus number */
+
+typedef enum {
+ GSBI_BUS_5 = 0,
+ GSBI_BUS_6,
+ GSBI_BUS_7,
+} spi_gsbi_bus_num;
+
+/* SPI Chip selects */
+
+typedef enum {
+ SPI_CS_0 ,
+ SPI_CS_1,
+ SPI_CS_2,
+ SPI_CS_3,
+} spi_cs;
+
+/* Flash Types */
+
+typedef enum {
+ ONLY_NAND,
+ ONLY_NOR,
+ NAND_NOR,
+ NOR_MMC,
+} flash_desc;
+
+#define NO_OF_DBG_UART_GPIOS 2
+
+#define SPI_NOR_FLASH_VENDOR_MICRON 0x1
+#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2
+
+/* SPI parameters */
+
+typedef struct {
+ spi_mode mode;
+ spi_gsbi_bus_num bus_number;
+ spi_cs chip_select;
+ int vendor;
+} spinorflash_params_t;
+
+typedef struct {
+ unsigned count;
+ uint8_t addr[7];
+} ipq_gmac_phy_addr_t;
+
+typedef struct {
+ unsigned base;
+ int unit;
+ unsigned is_macsec;
+ unsigned mac_pwr0;
+ unsigned mac_pwr1;
+ unsigned mac_conn_to_phy;
+ phy_interface_t phy;
+ ipq_gmac_phy_addr_t phy_addr;
+} ipq_gmac_board_cfg_t;
+
+#define IPQ_GMAC_NMACS 4
+
+enum gale_board_id {
+ BOARD_ID_PROTO_0 = 0,
+ BOARD_ID_PROTO_0_2 = 1,
+ BOARD_ID_WHIRLWIND = 2,
+ BOARD_ID_WHIRLWIND_SP5 = 3,
+ BOARD_ID_PROTO_0_2_NAND = 26,
+};
+
+/* Board specific parameters */
+typedef struct {
+#if 0
+ unsigned int gmac_gpio_count;
+ gpio_func_data_t *gmac_gpio;
+ ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS];
+ flash_desc flashdesc;
+ spinorflash_params_t flash_param;
+#endif
+} __attribute__ ((__packed__)) board_ipq40xx_params_t;
+
+extern board_ipq40xx_params_t *gboard_param;
+
+#if 0
+static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
+{
+ /*
+ * 'cfg' is valid if and only if
+ * unit number is non-negative and less than IPQ_GMAC_NMACS.
+ * 'cfg' pointer lies within the array range of
+ * board_ipq40xx_params_t->gmac_cfg[]
+ */
+ return ((cfg >= &gboard_param->gmac_cfg[0]) &&
+ (cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) &&
+ (cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS));
+}
+#endif
+
+unsigned int get_board_index(unsigned machid);
+void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count);
+
+void board_nand_init(void);
+
+#endif /* _IPQ40XX_CDP_H_ */
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/clock.h b/src/soc/qualcomm/ipq40xx/include/soc/clock.h
new file mode 100644
index 0000000000..51cc228c71
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/clock.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
+ * Source : APQ8064 LK Boot
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IPQ40XX_CLOCK_H_
+#define __IPQ40XX_CLOCK_H_
+
+#include <soc/iomap.h>
+
+/* UART clock @ 7.3728 MHz */
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+
+/* UART specific definitions */
+
+#define Uart_ns_val NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, \
+ 5, 4, 3, 1, 2, 0, 3)
+#define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | \
+ BM(BIT_POS_6, BIT_POS_0))
+#define Uart_mnd_en_mask (BIT(8) * !!(625))
+#define Uart_en_mask BIT(11)
+#define MD16(m, n) (BVAL(BIT_POS_31, BIT_POS_16, m) | \
+ BVAL(BIT_POS_15, BIT_POS_0, ~(n)))
+#define Uart_ns_val_rumi NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, \
+ 5, 4, 3, 1, 2, 0, 0)
+#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
+#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
+#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
+#define BB_PLL_ENA_SC0_REG REG(0x34C0)
+#define BB_PLL8_STATUS_REG REG(0x3158)
+#define REG(off) ((void *)(MSM_CLK_CTL_BASE + (off)))
+#define PLL8_STATUS_BIT 16
+
+#define PLL_LOCK_DET_STATUS_REG REG(0x03420)
+#define SFAB_AHB_S3_FCLK_CTL_REG REG(0x0216C)
+#define CFPB_CLK_NS_REG REG(0x0264C)
+#define CFPB0_HCLK_CTL_REG REG(0x02650)
+#define SFAB_CFPB_S_HCLK_CTL_REG REG(0x026C0)
+#define CFPB_SPLITTER_HCLK_CTL_REG REG(0x026E0)
+#define EBI2_CLK_CTL_REG REG(0x03B00)
+
+#define USB30_MASTER_CLK_CTL_REG REG(0x3b24)
+#define USB30_MASTER_CLK_MD REG(0x3b28)
+#define USB30_MASTER_CLK_NS REG(0x3b2c)
+#define USB30_1_MASTER_CLK_CTL_REG REG(0x3b34)
+#define USB30_MOC_UTMI_CLK_MD REG(0x3b40)
+#define USB30_MOC_UTMI_CLK_NS REG(0x3b44)
+#define USB30_MOC_UTMI_CLK_CTL REG(0x3b48)
+#define USB30_1_MOC_UTMI_CLK_CTL REG(0x3b4c)
+#define USB30_RESET REG(0x3b50)
+
+#define ALWAYS_ON_CLK_BRANCH_ENA(i) ((i) << 8)
+
+#define CLK_BRANCH_ENA_MASK 0x00000010
+#define CLK_BRANCH_ENA_ENABLE 0x00000010
+#define CLK_BRANCH_ENA_DISABLE 0x00000000
+#define CLK_BRANCH_ENA(i) ((i) << 4)
+
+/* Register: CFPB_CLK_NS */
+#define CLK_DIV_MASK 0x00000003
+#define CLK_DIV_DIV_1 0x00000000
+#define CLK_DIV_DIV_2 0x00000001
+#define CLK_DIV_DIV_3 0x00000002
+#define CLK_DIV_DIV_4 0x00000003
+#define CLK_DIV(i) ((i) << 0)
+
+#define MN_MODE_DUAL_EDGE 0x2
+#define BIT_POS_31 31
+#define BIT_POS_16 16
+#define BIT_POS_6 6
+#define BIT_POS_0 0
+#define BIT_POS_15 15
+
+#define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l)
+#define BVAL(m, l, val) (((val) << l) & BM(m, l))
+
+/* MD Registers */
+#define MD4(m_lsb, m, n_lsb, n) \
+ (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
+
+#define MD8(m_lsb, m, n_lsb, n) \
+ (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
+
+/* NS Registers */
+#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
+ (BVAL(n_msb, n_lsb, ~(n-m)) \
+ | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
+ | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
+
+#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
+ (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
+ | BVAL(s_msb, s_lsb, s))
+
+#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
+ (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
+
+#define NS_DIV(d_msb , d_lsb, d) \
+ BVAL(d_msb, d_lsb, (d-1))
+
+#define NS_SRC_SEL(s_msb, s_lsb, s) \
+ BVAL(s_msb, s_lsb, s)
+
+#define GMAC_AHB_RESET 0x903E24
+
+#define SRC_SEL_PLL0 (0x2 << 0)
+#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5)
+#define MNCNTR_ENABLE (0x1 << 8)
+#define MNCNTR_RST_ACTIVE (0x1 << 7)
+#define N_VAL 15
+
+#define GMAC_CORE_RESET(n) \
+ ((void *)(0x903CBC + ((n) * 0x20)))
+
+#define GMACSEC_CORE_RESET(n) \
+ ((void *)(0x903E28 + ((n - 1) * 4)))
+
+#define GMAC_COREn_CLCK_SRC_CTL(N) \
+ (0x00900000 + (0x3CA0 + (32*(N-1))))
+
+#define GMAC_COREn_CLCK_SRC0_MD(N) \
+ (0x00900000 + (0x3CA4 + (32*(N-1))))
+
+#define GMAC_COREn_CLCK_SRC1_MD(N) \
+ (0x00900000 + (0x3CA8 + (32*(N-1))))
+
+#define GMAC_COREn_CLCK_SRC0_NS(N) \
+ (0x00900000 + (0x3CAC + (32*(N-1))))
+
+#define GMAC_COREn_CLCK_SRC1_NS(N) \
+ (0x00900000 + (0x3CB0 + (32*(N-1))))
+
+#define DISABLE_DUAL_MN8_SEL (0)
+#define DISABLE_CLK_LOW_PWR (0 << 2)
+#define GMAC_CORE_CLCK_ROOT_ENABLE (1 << 1)
+
+/* GMAC_COREn_CLK_SRC[0,1]_MD register bits (Assuming 133MHz) */
+#define GMAC_CORE_CLCK_M 0x32
+#define GMAC_CORE_CLCK_D 0 /* NOT(2*D) value */
+#define GMAC_CORE_CLCK_M_SHIFT 16
+#define GMAC_CORE_CLCK_D_SHIFT 0
+#define GMAC_CORE_CLCK_M_VAL \
+ (GMAC_CORE_CLCK_M << GMAC_CORE_CLCK_M_SHIFT)
+#define GMAC_CORE_CLCK_D_VAL \
+ (GMAC_CORE_CLCK_D << GMAC_CORE_CLCK_D_SHIFT)
+
+/* GMAC_COREn_CLK_SRC[0,1]_NS register bits (Assuming 133MHz) */
+#define GMAC_CORE_CLCK_N 0x4 /* NOT(N-M) value, N=301 */
+#define GMAC_CORE_CLCK_N_SHIFT 16
+#define GMAC_CORE_CLCK_N_VAL \
+ (GMAC_CORE_CLCK_N << GMAC_CORE_CLCK_N_SHIFT)
+/* Enable M/N counter */
+#define GMAC_CORE_CLCK_MNCNTR_EN 0x00000100
+/* Activate reset for M/N counter */
+#define GMAC_CORE_CLCK_MNCNTR_RST 0x00000080
+/* M/N counter mode mask */
+#define GMAC_CORE_CLCK_MNCNTR_MODE_MASK 0x00000060
+#define GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT 5
+/* M/N counter mode dual-edge */
+#define GMAC_CORE_CLCK_MNCNTR_MODE_DUAL \
+ (2 << GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT)
+/* Pre divider select mask */
+#define GMAC_CORE_CLCK_PRE_DIV_SEL_MASK 0x00000018
+#define GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT 3
+/* Pre divider bypass */
+#define GMAC_CORE_CLCK_PRE_DIV_SEL_BYP \
+ (0 << GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT)
+/* clk source Mux select mask */
+#define GMAC_CORE_CLCK_SRC_SEL_MASK 0x00000007
+#define GMAC_CORE_CLCK_SRC_SEL_SHIFT 0
+/* output of clk source Mux is PLL0 */
+#define GMAC_CORE_CLCK_SRC_SEL_PLL0 \
+ (2 << GMAC_CORE_CLCK_SRC_SEL_SHIFT)
+#define GMAC_COREn_CLCK_CTL(N) \
+ (0x00900000 + (0x3CB4 + (32*(N-1))))
+
+#define GMAC_COREn_CLCK_INV_DISABLE (0 << 5)
+#define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4)
+
+
+/* Uart specific clock settings */
+
+void uart_pll_vote_clk_enable(unsigned int);
+void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n,
+ unsigned int d, unsigned int clk_dummy);
+void nand_clock_config(void);
+void usb_clock_config(void);
+int audio_clock_config(unsigned frequency);
+
+#endif /* __PLATFORM_IPQ40XX_CLOCK_H_ */
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/ebi2.h b/src/soc/qualcomm/ipq40xx/include/soc/ebi2.h
new file mode 100644
index 0000000000..1cc04aefad
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/ebi2.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2012 The Linux Foundation. All rights reserved.
+ *
+ * Taken from U-Boot.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __SOC_QUALCOMM_IPQ40XX_EBI2_H_
+#define __SOC_QUALCOMM_IPQ40XX_EBI2_H_
+
+#define EBI2CR_BASE (0x1A600000)
+
+struct ebi2cr_regs {
+ uint32_t chip_select_cfg0; /* 0x00000000 */
+ uint32_t cfg; /* 0x00000004 */
+ uint32_t hw_info; /* 0x00000008 */
+ uint8_t reserved0[20];
+ uint32_t lcd_cfg0; /* 0x00000020 */
+ uint32_t lcd_cfg1; /* 0x00000024 */
+ uint8_t reserved1[8];
+ uint32_t arbiter_cfg; /* 0x00000030 */
+ uint8_t reserved2[28];
+ uint32_t debug_sel; /* 0x00000050 */
+ uint32_t crc_cfg; /* 0x00000054 */
+ uint32_t crc_reminder_cfg; /* 0x00000058 */
+ uint32_t nand_adm_mux; /* 0x0000005C */
+ uint32_t mutex_addr_offset; /* 0x00000060 */
+ uint32_t misr_value; /* 0x00000064 */
+ uint32_t clkon_cfg; /* 0x00000068 */
+ uint32_t core_clkon_cfg; /* 0x0000006C */
+};
+
+/* Register: EBI2_CHIP_SELECT_CFG0 */
+#define CS7_CFG_MASK 0x00001000
+#define CS7_CFG_DISABLE 0x00000000
+#define CS7_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00001000
+#define CS7_CFG(i) ((i) << 12)
+
+#define CS6_CFG_MASK 0x00000800
+#define CS6_CFG_DISABLE 0x00000000
+#define CS6_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000800
+#define CS6_CFG(i) ((i) << 11)
+
+#define ETM_CS_CFG_MASK 0x00000400
+#define ETM_CS_CFG_DISABLE 0x00000000
+#define ETM_CS_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000400
+#define ETM_CS_CFG(i) ((i) << 10)
+
+#define CS5_CFG_MASK 0x00000300
+#define CS5_CFG_DISABLE 0x00000000
+#define CS5_CFG_LCD_DEVICE_CONNECTED 0x00000100
+#define CS5_CFG_LCD_DEVICE_CHIP_ENABLE 0x00000200
+#define CS5_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000300
+#define CS5_CFG(i) ((i) << 8)
+
+#define CS4_CFG_MASK 0x000000c0
+#define CS4_CFG_DISABLE 0x00000000
+#define CS4_CFG_LCD_DEVICE_CONNECTED 0x00000040
+#define CS4_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x000000C0
+#define CS4_CFG(i) ((i) << 6)
+
+#define CS3_CFG_MASK 0x00000020
+#define CS3_CFG_DISABLE 0x00000000
+#define CS3_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000020
+#define CS3_CFG(i) ((i) << 5)
+
+#define CS2_CFG_MASK 0x00000010
+#define CS2_CFG_DISABLE 0x00000000
+#define CS2_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000010
+#define CS2_CFG(i) ((i) << 4)
+
+#define CS1_CFG_MASK 0x0000000c
+#define CS1_CFG_DISABLE 0x00000000
+#define CS1_CFG_SERIAL_FLASH_DEVICE 0x00000004
+#define CS1_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000008
+#define CS1_CFG(i) ((i) << 2)
+
+#define CS0_CFG_MASK 0x00000003
+#define CS0_CFG_DISABLE 0x00000000
+#define CS0_CFG_SERIAL_FLASH_DEVICE 0x00000001
+#define CS0_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000002
+#define CS0_CFG(i) ((i) << 0)
+
+#endif
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h
new file mode 100644
index 0000000000..6304f71757
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2012 The Linux Foundation. All rights reserved.
+ * Source : APQ8064 LK Boot
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SOC_QUALCOMM_IPQ40XX_GPIO_H_
+#define __SOC_QUALCOMM_IPQ40XX_GPIO_H_
+
+#include <types.h>
+
+#define GPIO_FUNC_ENABLE 1
+#define GPIO_FUNC_DISABLE 0
+#define FUNC_SEL_1 1
+#define FUNC_SEL_3 3
+#define FUNC_SEL_GPIO 0
+#define GPIO_DRV_STR_10MA 0x4
+#define GPIO_DRV_STR_11MA 0x7
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT 0
+#define GPIO_OUTPUT 1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL 0
+#define GPIO_PULL_DOWN 1
+#define GPIO_KEEPER 2
+#define GPIO_PULL_UP 3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA 0
+#define GPIO_4MA 1
+#define GPIO_6MA 2
+#define GPIO_8MA 3
+#define GPIO_10MA 4
+#define GPIO_12MA 5
+#define GPIO_14MA 6
+#define GPIO_16MA 7
+
+/* GPIO TLMM: Status */
+#define GPIO_DISABLE 0
+#define GPIO_ENABLE 1
+
+/* GPIO MAX Valid # */
+#define GPIO_MAX_NUM 68
+
+/* GPIO TLMM: Mask */
+#define GPIO_CFG_PULL_MASK 0x3
+#define GPIO_CFG_FUNC_MASK 0xF
+#define GPIO_CFG_DRV_MASK 0x7
+#define GPIO_CFG_OE_MASK 0x1
+
+/* GPIO TLMM: Shift */
+#define GPIO_CFG_PULL_SHIFT 0
+#define GPIO_CFG_FUNC_SHIFT 2
+#define GPIO_CFG_DRV_SHIFT 6
+#define GPIO_CFG_OE_SHIFT 9
+
+/* GPIO IO: Mask */
+#define GPIO_IO_IN_MASK 0x1
+#define GPIO_IO_OUT_MASK 0x1
+
+/* GPIO IO: Shift */
+#define GPIO_IO_IN_SHIFT 0
+#define GPIO_IO_OUT_SHIFT 1
+
+typedef u32 gpio_t;
+
+void gpio_tlmm_config_set(gpio_t gpio, unsigned int func,
+ unsigned int pull, unsigned int drvstr,
+ unsigned int enable);
+
+void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func,
+ unsigned int *pull, unsigned int *drvstr,
+ unsigned int *enable);
+
+void gpio_io_config_set(gpio_t gpio, unsigned int out);
+
+/* Keep this to maintain backwards compatibility with the vendor API. */
+static inline void gpio_tlmm_config(unsigned int gpio, unsigned int func,
+ unsigned int dir, unsigned int pull,
+ unsigned int drvstr, unsigned int enable)
+{
+ gpio_tlmm_config_set(gpio, func, pull, drvstr, enable);
+}
+#endif // __SOC_QUALCOMM_IPQ40XX_GPIO_H_
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/gsbi.h b/src/soc/qualcomm/ipq40xx/include/soc/gsbi.h
new file mode 100644
index 0000000000..f2c375df0f
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/gsbi.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2011-2012 The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __GSBI_H_
+#define __GSBI_H_
+
+/* GSBI Registers */
+#define GSBI_CTRL_REG(base) ((base) + 0x0)
+
+#define GSBI_CTRL_REG_PROTOCOL_CODE_S 4
+#define GSBI_PROTOCOL_CODE_I2C 0x2
+#define GSBI_PROTOCOL_CODE_SPI 0x3
+#define GSBI_PROTOCOL_CODE_UART_FLOW 0x4
+#define GSBI_PROTOCOL_CODE_I2C_UART 0x6
+
+#define GSBI_HCLK_CTL_S 4
+#define GSBI_HCLK_CTL_CLK_ENA 0x1
+
+typedef enum {
+ GSBI_ID_1 = 1,
+ GSBI_ID_2,
+ GSBI_ID_3,
+ GSBI_ID_4,
+ GSBI_ID_5,
+ GSBI_ID_6,
+ GSBI_ID_7,
+} gsbi_id_t;
+
+typedef enum {
+ GSBI_SUCCESS = 0,
+ GSBI_ID_ERROR,
+ GSBI_ERROR,
+ GSBI_UNSUPPORTED
+} gsbi_return_t;
+
+typedef enum {
+ GSBI_PROTO_I2C_UIM = 1,
+ GSBI_PROTO_I2C_ONLY,
+ GSBI_PROTO_SPI_ONLY,
+ GSBI_PROTO_UART_FLOW_CTL,
+ GSBI_PROTO_UIM,
+ GSBI_PROTO_I2C_UART,
+} gsbi_protocol_t;
+
+gsbi_return_t gsbi_init(gsbi_id_t gsbi_id, gsbi_protocol_t protocol);
+int gsbi_init_board(gsbi_id_t gsbi_id);
+
+#endif
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
new file mode 100644
index 0000000000..543356dcbc
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2012 - 2013, 2015 The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __SOC_QUALCOMM_IPQ40XX_IOMAP_H_
+#define __SOC_QUALCOMM_IPQ40XX_IOMAP_H_
+
+#include <arch/io.h>
+#include <soc/cdp.h>
+
+/* Typecast to allow integers being passed as address
+ This needs to be included because vendor code is not compliant with our
+ macros for read/write. Hence, special macros for readl_i and writel_i are
+ included to do this in one place for all occurrences in vendor code
+ */
+#define readl_i(a) read32((const void *)(a))
+#define writel_i(v,a) write32((void *)a, v)
+#define clrsetbits_le32_i(addr, clear, set) \
+ clrsetbits_le32(((void *)(addr)), (clear), (set))
+
+#define MSM_CLK_CTL_BASE ((void *)0x00900000)
+
+#define MSM_TMR_BASE ((void *)0x0200A000)
+#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04)
+#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
+
+#define GPT_REG(off) (MSM_GPT_BASE + (off))
+#define DGT_REG(off) (MSM_DGT_BASE + (off))
+
+#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040)
+#define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038)
+#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C)
+#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C)
+
+#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820)
+
+#define GPT_MATCH_VAL GPT_REG(0x0000)
+#define GPT_COUNT_VAL GPT_REG(0x0004)
+#define GPT_ENABLE GPT_REG(0x0008)
+#define GPT_CLEAR GPT_REG(0x000C)
+
+#define GPT1_MATCH_VAL GPT_REG(0x00010)
+#define GPT1_COUNT_VAL GPT_REG(0x00014)
+#define GPT1_ENABLE GPT_REG(0x00018)
+#define GPT1_CLEAR GPT_REG(0x0001C)
+
+#define DGT_MATCH_VAL DGT_REG(0x0000)
+#define DGT_COUNT_VAL DGT_REG(0x0004)
+#define DGT_ENABLE DGT_REG(0x0008)
+#define DGT_CLEAR DGT_REG(0x000C)
+#define DGT_CLK_CTL DGT_REG(0x0010)
+
+/* RPM interface constants */
+#define RPM_INT ((void *)0x63020)
+#define RPM_INT_ACK ((void *)0x63060)
+#define RPM_SIGNAL_COOKIE ((void *)0x47C20)
+#define RPM_SIGNAL_ENTRY ((void *)0x47C24)
+#define RPM_FW_MAGIC_NUM 0x4D505242
+
+#define TLMM_BASE_ADDR ((void *)0x00800000)
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4)
+
+/* Yes, this is not a typo... host2 is actually mapped before host1. */
+#define USB_HOST2_XHCI_BASE 0x10000000
+#define USB_HOST2_DWC3_BASE 0x1000C100
+#define USB_HOST2_PHY_BASE 0x100F8800
+#define USB_HOST1_XHCI_BASE 0x11000000
+#define USB_HOST1_DWC3_BASE 0x1100C100
+#define USB_HOST1_PHY_BASE 0x110F8800
+
+#define GSBI_4 4
+#define UART1_DM_BASE 0x12450000
+#define UART_GSBI1_BASE 0x12440000
+#define UART2_DM_BASE 0x12490000
+#define UART_GSBI2_BASE 0x12480000
+#define UART4_DM_BASE 0x16340000
+#define UART_GSBI4_BASE 0x16300000
+
+#define UART2_DM_BASE 0x12490000
+#define UART_GSBI2_BASE 0x12480000
+
+#define GSBI1_BASE ((void *)0x12440000)
+#define GSBI2_BASE ((void *)0x12480000)
+#define GSBI3_BASE ((void *)0x16200000)
+#define GSBI4_BASE ((void *)0x16300000)
+#define GSBI5_BASE ((void *)0x1A200000)
+#define GSBI6_BASE ((void *)0x16500000)
+#define GSBI7_BASE ((void *)0x16600000)
+
+#define GSBI1_CTL_REG (GSBI1_BASE + (0x0))
+#define GSBI2_CTL_REG (GSBI2_BASE + (0x0))
+#define GSBI3_CTL_REG (GSBI3_BASE + (0x0))
+#define GSBI4_CTL_REG (GSBI4_BASE + (0x0))
+#define GSBI5_CTL_REG (GSBI5_BASE + (0x0))
+#define GSBI6_CTL_REG (GSBI6_BASE + (0x0))
+#define GSBI7_CTL_REG (GSBI7_BASE + (0x0))
+
+#define GSBI_QUP1_BASE (GSBI1_BASE + 0x20000)
+#define GSBI_QUP2_BASE (GSBI2_BASE + 0x20000)
+#define GSBI_QUP3_BASE (GSBI3_BASE + 0x80000)
+#define GSBI_QUP4_BASE (GSBI4_BASE + 0x80000)
+#define GSBI_QUP5_BASE (GSBI5_BASE + 0x80000)
+#define GSBI_QUP6_BASE (GSBI6_BASE + 0x80000)
+#define GSBI_QUP7_BASE (GSBI7_BASE + 0x80000)
+
+#define GSBI_CTL_PROTO_I2C 2
+#define GSBI_CTL_PROTO_CODE_SFT 4
+#define GSBI_CTL_PROTO_CODE_MSK 0x7
+#define GSBI_HCLK_CTL_GATE_ENA 6
+#define GSBI_HCLK_CTL_BRANCH_ENA 4
+#define GSBI_QUP_APPS_M_SHFT 16
+#define GSBI_QUP_APPS_M_MASK 0xFF
+#define GSBI_QUP_APPS_D_SHFT 0
+#define GSBI_QUP_APPS_D_MASK 0xFF
+#define GSBI_QUP_APPS_N_SHFT 16
+#define GSBI_QUP_APPS_N_MASK 0xFF
+#define GSBI_QUP_APPS_ROOT_ENA_SFT 11
+#define GSBI_QUP_APPS_BRANCH_ENA_SFT 9
+#define GSBI_QUP_APPS_MNCTR_EN_SFT 8
+#define GSBI_QUP_APPS_MNCTR_MODE_MSK 0x3
+#define GSBI_QUP_APPS_MNCTR_MODE_SFT 5
+#define GSBI_QUP_APPS_PRE_DIV_MSK 0x3
+#define GSBI_QUP_APPS_PRE_DIV_SFT 3
+#define GSBI_QUP_APPS_SRC_SEL_MSK 0x7
+
+
+#define GSBI_QUP_APSS_MD_REG(gsbi_n) ((MSM_CLK_CTL_BASE + 0x29c8) + \
+ (32*(gsbi_n-1)))
+#define GSBI_QUP_APSS_NS_REG(gsbi_n) ((MSM_CLK_CTL_BASE + 0x29cc) + \
+ (32*(gsbi_n-1)))
+#define GSBI_HCLK_CTL(n) ((MSM_CLK_CTL_BASE + 0x29C0) + \
+ (32*(n-1)))
+#endif // __SOC_QUALCOMM_IPQ40XX_IOMAP_H_
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/ipq_timer.h b/src/soc/qualcomm/ipq40xx/include/soc/ipq_timer.h
new file mode 100644
index 0000000000..0d0f9d2942
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/ipq_timer.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define TIMER_LOAD_VAL 0x21
+
+#define GPT_ENABLE_CLR_ON_MATCH_EN 2
+#define GPT_ENABLE_EN 1
+#define DGT_ENABLE_CLR_ON_MATCH_EN 2
+#define DGT_ENABLE_EN 1
+
+#define SPSS_TIMER_STATUS_DGT_EN (1 << 0)
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h b/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h
new file mode 100644
index 0000000000..25a06bff93
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h
@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2012 The Linux Foundation. All rights reserved.*
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __UART_DM_H__
+#define __UART_DM_H__
+
+#define PERIPH_BLK_BLSP 0
+
+#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
+ ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos)))
+
+extern void __udelay(unsigned long usec);
+
+
+enum MSM_BOOT_UART_DM_PARITY_MODE {
+ MSM_BOOT_UART_DM_NO_PARITY,
+ MSM_BOOT_UART_DM_ODD_PARITY,
+ MSM_BOOT_UART_DM_EVEN_PARITY,
+ MSM_BOOT_UART_DM_SPACE_PARITY
+};
+
+/* UART Stop Bit Length */
+enum MSM_BOOT_UART_DM_STOP_BIT_LEN {
+ MSM_BOOT_UART_DM_SBL_9_16,
+ MSM_BOOT_UART_DM_SBL_1,
+ MSM_BOOT_UART_DM_SBL_1_9_16,
+ MSM_BOOT_UART_DM_SBL_2
+};
+
+/* UART Bits per Char */
+enum MSM_BOOT_UART_DM_BITS_PER_CHAR {
+ MSM_BOOT_UART_DM_5_BPS,
+ MSM_BOOT_UART_DM_6_BPS,
+ MSM_BOOT_UART_DM_7_BPS,
+ MSM_BOOT_UART_DM_8_BPS
+};
+
+/* 8-N-1 Configuration */
+#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \
+ (MSM_BOOT_UART_DM_SBL_1 << 2) | \
+ (MSM_BOOT_UART_DM_8_BPS << 4))
+
+/* UART_DM Registers */
+
+/* UART Operational Mode Register */
+#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00)
+#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04)
+#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
+#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
+
+/* UART Clock Selection Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0)
+#else
+#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08)
+#endif
+
+/* UART DM TX FIFO Registers - 4 */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x)))
+#else
+#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x)))
+#endif
+
+/* UART Command Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8)
+#else
+#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10)
+#endif
+#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
+#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
+#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
+#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3)
+
+/* UART Channel Command */
+#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
+#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4) << 11)
+#define MSM_BOOT_UART_DM_CR_CH_CMD(x) \
+ (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
+#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0)
+#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1)
+#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2)
+#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3)
+#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4)
+#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5)
+#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6)
+#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7)
+#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8)
+#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9)
+#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C)
+#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D)
+#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E)
+#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10)
+#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11)
+#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12)
+#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13)
+#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14)
+
+/*UART General Command */
+#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8)
+
+#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0)
+#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1)
+#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2)
+#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3)
+#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4)
+#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5)
+#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
+
+/* UART Interrupt Mask Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0)
+#else
+#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14)
+#endif
+
+#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
+#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
+#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
+#define MSM_BOOT_UART_DM_RXSTALE (1 << 3)
+#define MSM_BOOT_UART_DM_RXLEV (1 << 4)
+#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5)
+#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6)
+#define MSM_BOOT_UART_DM_TX_READY (1 << 7)
+#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8)
+#define MSM_BOOT_UART_DM_TX_DONE (1 << 9)
+#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10)
+#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11)
+#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
+
+#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \
+ MSM_BOOT_UART_DM_TXLEV | \
+ MSM_BOOT_UART_DM_RXSTALE)
+
+/* UART Interrupt Programming Register */
+#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18)
+#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
+#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */
+
+/* UART Transmit/Receive FIFO Watermark Register */
+#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C)
+/* Interrupt is generated when FIFO level is less than or equal to this value */
+#define MSM_BOOT_UART_DM_TFW_VALUE 0
+
+#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20)
+/*Interrupt generated when no of words in RX FIFO is greater than this value */
+#define MSM_BOOT_UART_DM_RFW_VALUE 0
+
+/* UART Hunt Character Register */
+#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24)
+
+/* Used for RX transfer initialization */
+#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34)
+
+/* Default DMRX value - any value bigger than FIFO size would be fine */
+#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
+
+/* Register to enable IRDA function */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8)
+#else
+#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38)
+#endif
+
+/* UART Data Mover Enable Register */
+#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C)
+
+/* Number of characters for Transmission */
+#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040)
+
+/* UART RX FIFO Base Address */
+#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44)
+
+/* UART Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4)
+#else
+#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008)
+#endif
+#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
+#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
+#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
+#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3)
+#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4)
+#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5)
+#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6)
+#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7)
+#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
+
+/* UART Receive FIFO Registers - 4 in numbers */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x)))
+#else
+#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x)))
+#endif
+
+/* UART Masked Interrupt Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC)
+#else
+#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10)
+#endif
+
+/* UART Interrupt Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4)
+#else
+#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14)
+#endif
+
+/* Number of characters received since the end of last RX transfer */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC)
+#else
+#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38)
+#endif
+
+/* UART TX FIFO Status Register */
+#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C)
+#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
+#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) \
+ MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
+#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
+#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) \
+ MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
+
+/* UART RX FIFO Status Register */
+#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50)
+#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
+#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) \
+ MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
+#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
+#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) \
+ MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
+
+/* Macros for Common Errors */
+#define MSM_BOOT_UART_DM_E_SUCCESS 0
+#define MSM_BOOT_UART_DM_E_FAILURE 1
+#define MSM_BOOT_UART_DM_E_TIMEOUT 2
+#define MSM_BOOT_UART_DM_E_INVAL 3
+#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
+#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
+
+void ipq40xx_uart_init(void);
+
+#endif /* __UART_DM_H__ */
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/lcc-reg.h b/src/soc/qualcomm/ipq40xx/include/soc/lcc-reg.h
new file mode 100644
index 0000000000..9cf375840f
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/lcc-reg.h
@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DRIVERS_CLOCK_IPQ40XX_LCC_REG_H__
+#define __DRIVERS_CLOCK_IPQ40XX_LCC_REG_H__
+
+#define MSM_GCC_BASE 0x00900000
+#define MSM_LPASS_LCC_BASE 0x28000000
+
+/* GCC APCS Configuration/Control */
+
+#define GCC_PLL_APCS_REG 0x34C0
+
+#define GCC_PLL_APCS_PLL4_MASK 0x10
+#define GCC_PLL_APCS_PLL4_SHIFT 4
+#define GCC_PLL_APCS_PLL4_ENABLE (1 << GCC_PLL_APCS_PLL4_SHIFT)
+
+/* LCC PLL0 Configuration/Control */
+
+#define LCC_PLL0_MODE_REG 0x00
+#define LCC_PLL0_L_REG 0x04
+#define LCC_PLL0_M_REG 0x08
+#define LCC_PLL0_N_REG 0x0C
+#define LCC_PLL0_CFG_REG 0x14
+#define LCC_PLL0_STAT_REG 0x18
+
+#define LCC_PLL0_MODE_FSM_RESET_MASK 0x200000
+#define LCC_PLL0_MODE_FSM_RESET_SHIFT 21
+#define LCC_PLL0_MODE_FSM_RESET_ASSERT (1 << LCC_PLL0_MODE_FSM_RESET_SHIFT)
+
+#define LCC_PLL0_MODE_FSM_VOTE_MASK 0x100000
+#define LCC_PLL0_MODE_FSM_VOTE_SHIFT 20
+#define LCC_PLL0_MODE_FSM_VOTE_ENABLE (1 << LCC_PLL0_MODE_FSM_VOTE_SHIFT)
+
+#define LCC_PLL0_MODE_BIAS_CNT_MASK 0xFC000
+#define LCC_PLL0_MODE_BIAS_CNT_SHIFT 14
+
+#define LCC_PLL0_MODE_LOCK_CNT_MASK 0x3F00
+#define LCC_PLL0_MODE_LOCK_CNT_SHIFT 8
+
+#define LCC_PLL0_MODE_XO_SEL_MASK 0x30
+#define LCC_PLL0_MODE_XO_SEL_SHIFT 4
+#define LCC_PLL0_MODE_XO_SEL_PXO (0 << LCC_PLL0_MODE_XO_SEL_SHIFT)
+#define LCC_PLL0_MODE_XO_SEL_MXO (1 << LCC_PLL0_MODE_XO_SEL_SHIFT)
+#define LCC_PLL0_MODE_XO_SEL_CXO (2 << LCC_PLL0_MODE_XO_SEL_SHIFT)
+
+#define LCC_PLL0_MODE_TEST_MASK 0x8
+#define LCC_PLL0_MODE_TEST_SHIFT 3
+#define LCC_PLL0_MODE_TEST_ENABLE (1 << LCC_PLL0_MODE_TEST_SHIFT)
+
+#define LCC_PLL0_MODE_RESET_MASK 0x4
+#define LCC_PLL0_MODE_RESET_SHIFT 2
+#define LCC_PLL0_MODE_RESET_DEASSERT (1 << LCC_PLL0_MODE_RESET_SHIFT)
+
+#define LCC_PLL0_MODE_BYPASS_MASK 0x2
+#define LCC_PLL0_MODE_BYPASS_SHIFT 1
+#define LCC_PLL0_MODE_BYPASS_DISABLE (1 << LCC_PLL0_MODE_BYPASS_SHIFT)
+
+#define LCC_PLL0_MODE_OUTPUT_MASK 0x1
+#define LCC_PLL0_MODE_OUTPUT_SHIFT 0
+#define LCC_PLL0_MODE_OUTPUT_ENABLE (1 << LCC_PLL0_MODE_OUTPUT_SHIFT)
+
+#define LCC_PLL0_L_MASK 0x3FF
+#define LCC_PLL0_L_SHIFT 0
+
+#define LCC_PLL0_M_MASK 0x7FFFF
+#define LCC_PLL0_M_SHIFT 0
+
+#define LCC_PLL0_N_MASK 0x7FFFF
+#define LCC_PLL0_N_SHIFT 0
+
+#define LCC_PLL0_CFG_LV_MAIN_MASK 0x800000
+#define LCC_PLL0_CFG_LV_MAIN_SHIFT 23
+#define LCC_PLL0_CFG_LV_MAIN_ENABLE (1 << LCC_PLL0_CFG_LV_MAIN_SHIFT)
+
+#define LCC_PLL0_CFG_FRAC_MASK 0x400000
+#define LCC_PLL0_CFG_FRAC_SHIFT 22
+#define LCC_PLL0_CFG_FRAC_ENABLE (1 << LCC_PLL0_CFG_FRAC_SHIFT)
+
+#define LCC_PLL0_CFG_POSTDIV_MASK 0x300000
+#define LCC_PLL0_CFG_POSTDIV_SHIFT 20
+#define LCC_PLL0_CFG_POSTDIV_DIV1 (0 << LCC_PLL0_CFG_POSTDIV_SHIFT)
+#define LCC_PLL0_CFG_POSTDIV_DIV2 (1 << LCC_PLL0_CFG_POSTDIV_SHIFT)
+#define LCC_PLL0_CFG_POSTDIV_DIV4 (2 << LCC_PLL0_CFG_POSTDIV_SHIFT)
+
+#define LCC_PLL0_CFG_PREDIV_MASK 0x80000
+#define LCC_PLL0_CFG_PREDIV_SHIFT 19
+#define LCC_PLL0_CFG_PREDIV_DIV1 (0 << LCC_PLL0_CFG_PREDIV_SHIFT)
+#define LCC_PLL0_CFG_PREDIV_DIV2 (1 << LCC_PLL0_CFG_PREDIV_SHIFT)
+
+#define LCC_PLL0_CFG_VCO_SEL_MASK 0x30000
+#define LCC_PLL0_CFG_VCO_SEL_SHIFT 16
+#define LCC_PLL0_CFG_VCO_SEL_LOW (0 << LCC_PLL0_CFG_VCO_SEL_SHIFT)
+#define LCC_PLL0_CFG_VCO_SEL_MED (1 << LCC_PLL0_CFG_VCO_SEL_SHIFT)
+#define LCC_PLL0_CFG_VCO_SEL_HIGH (2 << LCC_PLL0_CFG_VCO_SEL_SHIFT)
+
+#define LCC_PLL0_STAT_ACTIVE_MASK 0x10000
+#define LCC_PLL0_STAT_ACTIVE_SHIFT 16
+#define LCC_PLL0_STAT_ACTIVE_SET (1 << LCC_PLL0_STAT_ACTIVE_SHIFT)
+
+#define LCC_PLL0_STAT_NOCLK_MASK 0x1
+#define LCC_PLL0_STAT_NOCLK_SHIFT 0
+#define LCC_PLL0_STAT_NOCLK_SET (1 << LCC_PLL0_STAT_NOCLK_SHIFT)
+
+/* LCC AHBIX Configuration/Control */
+
+#define LCC_AHBIX_NS_REG 0x38
+#define LCC_AHBIX_MD_REG 0x3C
+#define LCC_AHBIX_STAT_REG 0x44
+
+#define LCC_AHBIX_NS_N_VAL_MASK 0xFF000000
+#define LCC_AHBIX_NS_N_VAL_SHIFT 24
+
+#define LCC_AHBIX_NS_CRC_MASK 0x800
+#define LCC_AHBIX_NS_CRC_SHIFT 11
+#define LCC_AHBIX_NS_CRC_ENABLE (1 << LCC_AHBIX_NS_CRC_SHIFT)
+
+#define LCC_AHBIX_NS_GFM_SEL_MASK 0x400
+#define LCC_AHBIX_NS_GFM_SEL_SHIFT 10
+#define LCC_AHBIX_NS_GFM_SEL_PXO (0 << LCC_AHBIX_NS_GFM_SEL_SHIFT)
+#define LCC_AHBIX_NS_GFM_SEL_MNC (1 << LCC_AHBIX_NS_GFM_SEL_SHIFT)
+
+#define LCC_AHBIX_NS_MNC_CLK_MASK 0x200
+#define LCC_AHBIX_NS_MNC_CLK_SHIFT 9
+#define LCC_AHBIX_NS_MNC_CLK_ENABLE (1 << LCC_AHBIX_NS_MNC_CLK_SHIFT)
+
+#define LCC_AHBIX_NS_MNC_MASK 0x100
+#define LCC_AHBIX_NS_MNC_SHIFT 8
+#define LCC_AHBIX_NS_MNC_ENABLE (1 << LCC_AHBIX_NS_MNC_SHIFT)
+
+#define LCC_AHBIX_NS_MNC_RESET_MASK 0x80
+#define LCC_AHBIX_NS_MNC_RESET_SHIFT 7
+#define LCC_AHBIX_NS_MNC_RESET_ASSERT (1 << LCC_AHBIX_NS_MNC_RESET_SHIFT)
+
+#define LCC_AHBIX_NS_MNC_MODE_MASK 0x60
+#define LCC_AHBIX_NS_MNC_MODE_SHIFT 5
+#define LCC_AHBIX_NS_MNC_MODE_BYPASS (0 << LCC_AHBIX_NS_MNC_MODE_SHIFT)
+#define LCC_AHBIX_NS_MNC_MODE_SWALLOW (1 << LCC_AHBIX_NS_MNC_MODE_SHIFT)
+#define LCC_AHBIX_NS_MNC_MODE_DUAL (2 << LCC_AHBIX_NS_MNC_MODE_SHIFT)
+#define LCC_AHBIX_NS_MNC_MODE_SINGLE (3 << LCC_AHBIX_NS_MNC_MODE_SHIFT)
+
+#define LCC_AHBIX_NS_PREDIV_MASK 0x18
+#define LCC_AHBIX_NS_PREDIV_SHIFT 3
+#define LCC_AHBIX_NS_PREDIV_BYPASS (0 << LCC_AHBIX_NS_PREDIV_SHIFT)
+#define LCC_AHBIX_NS_PREDIV_DIV2 (1 << LCC_AHBIX_NS_PREDIV_SHIFT)
+#define LCC_AHBIX_NS_PREDIV_DIV4 (3 << LCC_AHBIX_NS_PREDIV_SHIFT)
+
+#define LCC_AHBIX_NS_MN_SRC_MASK 0x7
+#define LCC_AHBIX_NS_MN_SRC_SHIFT 0
+#define LCC_AHBIX_NS_MN_SRC_PXO (0 << LCC_AHBIX_NS_MN_SRC_SHIFT)
+#define LCC_AHBIX_NS_MN_SRC_CXO (1 << LCC_AHBIX_NS_MN_SRC_SHIFT)
+#define LCC_AHBIX_NS_MN_SRC_LPA (2 << LCC_AHBIX_NS_MN_SRC_SHIFT)
+#define LCC_AHBIX_NS_MN_SRC_SEC (3 << LCC_AHBIX_NS_MN_SRC_SHIFT)
+#define LCC_AHBIX_NS_MN_SRC_CTEST (6 << LCC_AHBIX_NS_MN_SRC_SHIFT)
+#define LCC_AHBIX_NS_MN_SRC_PTEST (7 << LCC_AHBIX_NS_MN_SRC_SHIFT)
+
+#define LCC_AHBIX_MD_M_VAL_MASK 0xFF00
+#define LCC_AHBIX_MD_M_VAL_SHIFT 8
+
+#define LCC_AHBIX_MD_NOT_2D_VAL_MASK 0xFF
+#define LCC_AHBIX_MD_NOT_2D_VAL_SHIFT 0
+
+#define LCC_AHBIX_STAT_AHB_CLK_MASK 0x400
+#define LCC_AHBIX_STAT_AHB_CLK_SHIFT 10
+#define LCC_AHBIX_STAT_AHB_CLK_ON (1 << LCC_AHBIX_STAT_AHB_CLK_SHIFT)
+
+#define LCC_AHBIX_STAT_AIF_CLK_MASK 0x200
+#define LCC_AHBIX_STAT_AIF_CLK_SHIFT 9
+#define LCC_AHBIX_STAT_AIF_CLK_ON (1 << LCC_AHBIX_STAT_AIF_CLK_SHIFT)
+
+#define LCC_AHBIX_STAT_FAB2_CLK_MASK 0x40
+#define LCC_AHBIX_STAT_FAB2_CLK_SHIFT 6
+#define LCC_AHBIX_STAT_FAB2_CLK_ON (1 << LCC_AHBIX_STAT_FAB2_CLK_SHIFT)
+
+#define LCC_AHBIX_STAT_2FAB_CLK_MASK 0x20
+#define LCC_AHBIX_STAT_2FAB_CLK_SHIFT 5
+#define LCC_AHBIX_STAT_2FAB_CLK_ON (1 << LCC_AHBIX_STAT_2FAB_CLK_SHIFT)
+
+/* LCC MI2S Configuration/Control */
+
+#define LCC_MI2S_NS_REG 0x48
+#define LCC_MI2S_MD_REG 0x4C
+#define LCC_MI2S_STAT_REG 0x50
+
+#define LCC_MI2S_NS_N_VAL_MASK 0xFF000000
+#define LCC_MI2S_NS_N_VAL_SHIFT 24
+
+#define LCC_MI2S_NS_RESET_MASK 0x80000
+#define LCC_MI2S_NS_RESET_SHIFT 19
+#define LCC_MI2S_NS_RESET_ASSERT (1 << LCC_MI2S_NS_RESET_SHIFT)
+
+#define LCC_MI2S_NS_OSR_INV_MASK 0x40000
+#define LCC_MI2S_NS_OSR_INV_SHIFT 18
+#define LCC_MI2S_NS_OSR_INV_ENABLE (1 << LCC_MI2S_NS_OSR_INV_SHIFT)
+
+#define LCC_MI2S_NS_OSR_CXC_MASK 0x20000
+#define LCC_MI2S_NS_OSR_CXC_SHIFT 17
+#define LCC_MI2S_NS_OSR_CXC_ENABLE (1 << LCC_MI2S_NS_OSR_CXC_SHIFT)
+
+#define LCC_MI2S_NS_BIT_INV_MASK 0x10000
+#define LCC_MI2S_NS_BIT_INV_SHIFT 16
+#define LCC_MI2S_NS_BIT_INV_ENABLE (1 << LCC_MI2S_NS_BIT_INV_SHIFT)
+
+#define LCC_MI2S_NS_BIT_CXC_MASK 0x8000
+#define LCC_MI2S_NS_BIT_CXC_SHIFT 15
+#define LCC_MI2S_NS_BIT_CXC_ENABLE (1 << LCC_MI2S_NS_BIT_CXC_SHIFT)
+
+#define LCC_MI2S_NS_BIT_SRC_MASK 0x4000
+#define LCC_MI2S_NS_BIT_SRC_SHIFT 14
+#define LCC_MI2S_NS_BIT_SRC_MASTER (0 << LCC_MI2S_NS_BIT_SRC_SHIFT)
+#define LCC_MI2S_NS_BIT_SRC_SLAVE (1 << LCC_MI2S_NS_BIT_SRC_SHIFT)
+
+#define LCC_MI2S_NS_BIT_DIV_MASK 0x3C00
+#define LCC_MI2S_NS_BIT_DIV_SHIFT 10
+#define LCC_MI2S_NS_BIT_DIV_BYPASS (0 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV2 (1 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV3 (2 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV4 (3 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV5 (4 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV6 (5 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV7 (6 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV8 (7 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV9 (8 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV10 (9 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV11 (10 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV12 (11 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV13 (12 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV14 (13 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV15 (14 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+#define LCC_MI2S_NS_BIT_DIV_DIV16 (15 << LCC_MI2S_NS_BIT_DIV_SHIFT)
+
+#define LCC_MI2S_NS_MNC_CLK_MASK 0x200
+#define LCC_MI2S_NS_MNC_CLK_SHIFT 9
+#define LCC_MI2S_NS_MNC_CLK_ENABLE (1 << LCC_MI2S_NS_MNC_CLK_SHIFT)
+
+#define LCC_MI2S_NS_MNC_MASK 0x100
+#define LCC_MI2S_NS_MNC_SHIFT 8
+#define LCC_MI2S_NS_MNC_ENABLE (1 << LCC_MI2S_NS_MNC_SHIFT)
+
+#define LCC_MI2S_NS_MNC_RESET_MASK 0x80
+#define LCC_MI2S_NS_MNC_RESET_SHIFT 7
+#define LCC_MI2S_NS_MNC_RESET_ASSERT (1 << LCC_MI2S_NS_MNC_RESET_SHIFT)
+
+#define LCC_MI2S_NS_MNC_MODE_MASK 0x60
+#define LCC_MI2S_NS_MNC_MODE_SHIFT 5
+#define LCC_MI2S_NS_MNC_MODE_BYPASS (0 << LCC_MI2S_NS_MNC_MODE_SHIFT)
+#define LCC_MI2S_NS_MNC_MODE_SWALLOW (1 << LCC_MI2S_NS_MNC_MODE_SHIFT)
+#define LCC_MI2S_NS_MNC_MODE_DUAL (2 << LCC_MI2S_NS_MNC_MODE_SHIFT)
+#define LCC_MI2S_NS_MNC_MODE_SINGLE (3 << LCC_MI2S_NS_MNC_MODE_SHIFT)
+
+#define LCC_MI2S_NS_PREDIV_MASK 0x18
+#define LCC_MI2S_NS_PREDIV_SHIFT 3
+#define LCC_MI2S_NS_PREDIV_BYPASS (0 << LCC_MI2S_NS_PREDIV_SHIFT)
+#define LCC_MI2S_NS_PREDIV_DIV2 (1 << LCC_MI2S_NS_PREDIV_SHIFT)
+#define LCC_MI2S_NS_PREDIV_DIV4 (3 << LCC_MI2S_NS_PREDIV_SHIFT)
+
+#define LCC_MI2S_NS_MN_SRC_MASK 0x7
+#define LCC_MI2S_NS_MN_SRC_SHIFT 0
+#define LCC_MI2S_NS_MN_SRC_PXO (0 << LCC_MI2S_NS_MN_SRC_SHIFT)
+#define LCC_MI2S_NS_MN_SRC_CXO (1 << LCC_MI2S_NS_MN_SRC_SHIFT)
+#define LCC_MI2S_NS_MN_SRC_LPA (2 << LCC_MI2S_NS_MN_SRC_SHIFT)
+#define LCC_MI2S_NS_MN_SRC_SEC (3 << LCC_MI2S_NS_MN_SRC_SHIFT)
+#define LCC_MI2S_NS_MN_SRC_CTEST (6 << LCC_MI2S_NS_MN_SRC_SHIFT)
+#define LCC_MI2S_NS_MN_SRC_PTEST (7 << LCC_MI2S_NS_MN_SRC_SHIFT)
+
+#define LCC_MI2S_MD_M_VAL_MASK 0xFF00
+#define LCC_MI2S_MD_M_VAL_SHIFT 8
+
+#define LCC_MI2S_MD_NOT_2D_VAL_MASK 0xFF
+#define LCC_MI2S_MD_NOT_2D_VAL_SHIFT 0
+
+#define LCC_MI2S_STAT_OSR_CLK_MASK 0x2
+#define LCC_MI2S_STAT_OSR_CLK_SHIFT 1
+#define LCC_MI2S_STAT_OSR_CLK_ON (1 << LCC_MI2S_STAT_OSR_CLK_SHIFT)
+
+#define LCC_MI2S_STAT_BIT_CLK_MASK 0x1
+#define LCC_MI2S_STAT_BIT_CLK_SHIFT 0
+#define LCC_MI2S_STAT_BIT_CLK_ON (1 << LCC_MI2S_STAT_BIT_CLK_SHIFT)
+
+/* LCC PLL Configuration/Control */
+
+#define LCC_PLL_PCLK_REG 0xC4
+#define LCC_PLL_SCLK_REG 0xC8
+
+#define LCC_PLL_PCLK_RESET_MASK 0x2
+#define LCC_PLL_PCLK_RESET_SHIFT 1
+#define LCC_PLL_PCLK_RESET_ASSERT (1 << LCC_PLL_PCLK_RESET_SHIFT)
+
+#define LCC_PLL_PCLK_SRC_MASK 0x1
+#define LCC_PLL_PCLK_SRC_SHIFT 0
+#define LCC_PLL_PCLK_SRC_PXO (0 << LCC_PLL_PCLK_SRC_SHIFT)
+#define LCC_PLL_PCLK_SRC_PRI (1 << LCC_PLL_PCLK_SRC_SHIFT)
+
+#define LCC_PLL_SCLK_RESET_MASK 0x10
+#define LCC_PLL_SCLK_RESET_SHIFT 4
+#define LCC_PLL_SCLK_RESET_ASSERT (1 << LCC_PLL_SCLK_RESET_SHIFT)
+
+#define LCC_PLL_SCLK_DIV_MASK 0xC
+#define LCC_PLL_SCLK_DIV_SHIFT 2
+#define LCC_PLL_SCLK_DIV_BYPASS (0 << LCC_PLL_SCLK_DIV_SHIFT)
+#define LCC_PLL_SCLK_DIV_DIV2 (1 << LCC_PLL_SCLK_DIV_SHIFT)
+#define LCC_PLL_SCLK_DIV_DIV3 (2 << LCC_PLL_SCLK_DIV_SHIFT)
+#define LCC_PLL_SCLK_DIV_DIV4 (3 << LCC_PLL_SCLK_DIV_SHIFT)
+
+#define LCC_PLL_SCLK_XO_MASK 0x2
+#define LCC_PLL_SCLK_XO_SHIFT 1
+#define LCC_PLL_SCLK_XO_PXO (0 << LCC_PLL_SCLK_XO_SHIFT)
+#define LCC_PLL_SCLK_XO_SEC (1 << LCC_PLL_SCLK_XO_SHIFT)
+
+#define LCC_PLL_SCLK_MUX_MASK 0x1
+#define LCC_PLL_SCLK_MUX_SHIFT 0
+#define LCC_PLL_SCLK_MUX_PLL1 (0 << LCC_PLL_SCLK_MUX_SHIFT)
+#define LCC_PLL_SCLK_MUX_PLL0 (1 << LCC_PLL_SCLK_MUX_SHIFT)
+
+#endif /* __DRIVERS_CLOCK_IPQ40XX_LCC_REG_H__ */
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
new file mode 100644
index 0000000000..6ff2b77608
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+SECTIONS
+{
+ REGION(rpm, 0x00020000, 160K, 8K)
+ SRAM_START(0x2A000000)
+ /* This includes bootblock image, can be reused after bootblock starts */
+/* UBER_SBL(0x2A000000, 48K) */
+/* DDR(0x2A000000, 48K) */
+ BOOTBLOCK(0x2A00C000, 24K)
+ OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K)
+ VBOOT2_WORK(0x2A022000, 16K)
+ PRERAM_CBMEM_CONSOLE(0x2A026000, 32K)
+ TIMESTAMP(0x2A02E000, 1K)
+
+/* 0x2e400..0x3F000 67 KB free */
+
+/* Keep the below area reserved at all times, it is used by various QCA
+ components as shared data
+ QCA_SHARED_RAM(2A03F000, 4K)
+*/
+ STACK(0x2A040000, 16K)
+ PRERAM_CBFS_CACHE(0x2A044000, 93K)
+ TTB_SUBTABLES(0x2A05B800, 2K)
+ TTB(0x2A05C000, 16K)
+ SRAM_END(0x2A060000)
+
+ DRAM_START(0x40000000)
+ RAMSTAGE(0x40640000, 128K)
+ SYMBOL(memlayout_cbmem_top, 0x59F80000)
+ POSTRAM_CBFS_CACHE(0x59F80000, 384K)
+ DMA_COHERENT(0x5A000000, 2M)
+}
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/qup.h b/src/soc/qualcomm/ipq40xx/include/soc/qup.h
new file mode 100644
index 0000000000..d0186f59b0
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/qup.h
@@ -0,0 +1,219 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __QUP_H__
+#define __QUP_H__
+
+#include <soc/gsbi.h>
+
+/* QUP block registers */
+#define QUP_CONFIG 0x0
+#define QUP_STATE 0x4
+#define QUP_IO_MODES 0x8
+#define QUP_SW_RESET 0xc
+#define QUP_TIME_OUT 0x10
+#define QUP_TIME_OUT_CURRENT 0x14
+#define QUP_OPERATIONAL 0x18
+#define QUP_ERROR_FLAGS 0x1c
+#define QUP_ERROR_FLAGS_EN 0x20
+#define QUP_TEST_CTRL 0x24
+#define QUP_MX_OUTPUT_COUNT 0x100
+#define QUP_MX_OUTPUT_CNT_CURRENT 0x104
+#define QUP_OUTPUT_DEBUG 0x108
+#define QUP_OUTPUT_FIFO_WORD_CNT 0x10c
+#define QUP_OUTPUT_FIFO 0x110
+#define QUP_MX_WRITE_COUNT 0x150
+#define QUP_WRITE_CNT_CURRENT 0x154
+#define QUP_MX_INPUT_COUNT 0x200
+#define QUP_READ_COUNT 0x208
+#define QUP_MX_READ_CNT_CURRENT 0x20c
+#define QUP_INPUT_DEBUG 0x210
+#define QUP_INPUT_FIFO_WORD_CNT 0x214
+#define QUP_INPUT_FIFO 0x218
+#define QUP_I2C_MASTER_CLK_CTL 0x400
+#define QUP_I2C_MASTER_STATUS 0x404
+
+#define OUTPUT_FIFO_FULL (1<<6)
+#define INPUT_FIFO_NOT_EMPTY (1<<5)
+#define OUTPUT_FIFO_NOT_EMPTY (1<<4)
+#define INPUT_SERVICE_FLAG (1<<9)
+#define OUTPUT_SERVICE_FLAG (1<<8)
+#define QUP_OUTPUT_BIT_SHIFT_EN (1<<16)
+
+#define QUP_MODE_MASK (0x03)
+#define QUP_OUTPUT_MODE_SHFT (10)
+#define QUP_INPUT_MODE_SHFT (12)
+
+#define QUP_FS_DIVIDER_MASK (0xFF)
+
+#define QUP_MINI_CORE_PROTO_SHFT (8)
+#define QUP_MINI_CORE_PROTO_MASK (0x0F)
+
+/* Mini-core states */
+#define QUP_STATE_RESET 0x0
+#define QUP_STATE_RUN 0x1
+#define QUP_STATE_PAUSE 0x3
+#define QUP_STATE_VALID (1<<2)
+#define QUP_STATE_MASK 0x3
+#define QUP_STATE_VALID_MASK (1<<2)
+
+/* Tags for output FIFO */
+#define QUP_I2C_1CLK_NOOP_SEQ 0x1 /*MSB 8-bit NOP, LSB 8-bits 1 clk.*/
+#define QUP_I2C_START_SEQ (0x1 << 8)
+#define QUP_I2C_DATA_SEQ (0x2 << 8)
+#define QUP_I2C_STOP_SEQ (0x3 << 8)
+#define QUP_I2C_RECV_SEQ (0x4 << 8)
+
+/* Tags for input FIFO */
+#define QUP_I2C_MIDATA_SEQ (0x5 << 8)
+#define QUP_I2C_MISTOP_SEQ (0x6 << 8)
+#define QUP_I2C_MINACK_SEQ (0x7 << 8)
+
+#define QUP_I2C_ADDR(x) ((x & 0xFF) << 1)
+#define QUP_I2C_DATA(x) (x & 0xFF)
+#define QUP_I2C_MI_TAG(x) (x & 0xFF00)
+#define QUP_I2C_SLAVE_READ (0x1)
+
+/*Bit vals for I2C_MASTER_CLK_CTL register */
+#define QUP_HS_DIVIDER_SHFT (8)
+#define QUP_DIVIDER_MIN_VAL (0x3)
+
+/* Bit masks for I2C_MASTER_STATUS register */
+#define QUP_I2C_INVALID_READ_SEQ (1 << 25)
+#define QUP_I2C_INVALID_READ_ADDR (1 << 24)
+#define QUP_I2C_INVALID_TAG (1 << 23)
+#define QUP_I2C_FAILED_MASK (0x3 << 6)
+#define QUP_I2C_INVALID_WRITE (1 << 5)
+#define QUP_I2C_ARB_LOST (1 << 4)
+#define QUP_I2C_PACKET_NACK (1 << 3)
+#define QUP_I2C_BUS_ERROR (1 << 2)
+
+typedef enum {
+ QUP_SUCCESS = 0,
+ QUP_ERR_BAD_PARAM,
+ QUP_ERR_STATE_SET,
+ QUP_ERR_TIMEOUT,
+ QUP_ERR_UNSUPPORTED,
+ QUP_ERR_I2C_FAILED,
+ QUP_ERR_I2C_ARB_LOST,
+ QUP_ERR_I2C_BUS_ERROR,
+ QUP_ERR_I2C_INVALID_SLAVE_ADDR,
+ QUP_ERR_XFER_FAIL,
+ QUP_ERR_I2C_NACK,
+ QUP_ERR_I2C_INVALID_WRITE,
+ QUP_ERR_I2C_INVALID_TAG,
+ QUP_ERR_UNDEFINED,
+} qup_return_t;
+
+typedef enum {
+ QUP_MINICORE_SPI = 1,
+ QUP_MINICORE_I2C_MASTER,
+ QUP_MINICORE_I2C_SLAVE
+} qup_protocol_t;
+
+typedef enum {
+ QUP_MODE_FIFO = 0,
+ QUP_MODE_BLOCK,
+ QUP_MODE_DATAMOVER,
+} qup_mode_t;
+
+typedef struct {
+ qup_protocol_t protocol;
+ unsigned clk_frequency;
+ unsigned src_frequency;
+ qup_mode_t mode;
+ unsigned initialized;
+} qup_config_t;
+
+typedef struct {
+ qup_protocol_t protocol;
+ union {
+ struct {
+ uint8_t addr;
+ uint8_t *data;
+ unsigned data_len;
+ } iic;
+ struct {
+ void *in;
+ void *out;
+ unsigned size;
+ } spi;
+ } p;
+} qup_data_t;
+
+/*
+ * Initialize GSBI QUP block for FIFO I2C transfers.
+ * gsbi_id[IN]: GSBI for which QUP is to be initialized.
+ * config_ptr[IN]: configurations parameters for the QUP.
+ *
+ * return: QUP_SUCCESS, if initialization succeeds.
+ */
+qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr);
+
+/*
+ * Set QUP state to run, pause, reset.
+ * gsbi_id[IN]: GSBI block for which QUP state is to be set.
+ * state[IN]: New state to transition to.
+ *
+ * return: QUP_SUCCESS, if state transition succeeds.
+ */
+qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state);
+
+/*
+ * Reset the status bits set during an i2c transfer.
+ * gsbi_id[IN]: GSBI block for which i2c status bits are to be cleared.
+ *
+ * return: QUP_SUCCESS, if status bits are cleared successfully.
+ */
+qup_return_t qup_reset_i2c_master_status(gsbi_id_t gsbi_id);
+
+/*
+ * Send data to the peripheral on the bus.
+ * gsbi_id[IN]: GSBI block for which data is to be sent.
+ * p_tx_obj[IN]: Data to be sent to the slave on the bus.
+ * stop_seq[IN]: When set to non-zero QUP engine sends i2c stop sequnce.
+ *
+ * return: QUP_SUCCESS, when data is sent successfully to the peripheral.
+ */
+qup_return_t qup_send_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj,
+ uint8_t stop_seq);
+
+/*
+ * Receive data from peripheral on the bus.
+ * gsbi_id[IN]: GSBI block from which data is to be received.
+ * p_tx_obj[IN]: length of data to be received, slave address.
+ * [OUT]: buffer filled with data from slave.
+ *
+ * return: QUP_SUCCESS, when data is received successfully.
+ */
+qup_return_t qup_recv_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj);
+
+#endif //__QUP_H__
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h b/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h
new file mode 100644
index 0000000000..5ad11f1a10
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_SOC_SERVICES_H__
+#define __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_SOC_SERVICES_H__
+
+#include <types.h>
+
+extern u8 _memlayout_cbmem_top[];
+
+/* Returns zero on success, nonzero on failure. */
+int initialize_dram(void);
+
+/* Loads and runs TZBSP, switches into user mode. */
+void start_tzbsp(void);
+
+/* A helper function needed to start TZBSP properly. */
+int tz_init_wrapper(int, int, void *);
+
+/* Load RPM code into memory and trigger its execution. */
+void start_rpm(void);
+
+#endif
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/spi.h b/src/soc/qualcomm/ipq40xx/include/soc/spi.h
new file mode 100644
index 0000000000..8e52d62a01
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/spi.h
@@ -0,0 +1,305 @@
+/*
+ * Register definitions for the IPQ GSBI Controller
+ *
+ * Copyright (c) 2012 The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IPQ40XX_SPI_H_
+#define _IPQ40XX_SPI_H_
+
+#include <spi_flash.h>
+#include <soc/iomap.h>
+
+#define QUP5_BASE ((uint32_t)GSBI_QUP5_BASE)
+#define QUP6_BASE ((uint32_t)GSBI_QUP6_BASE)
+#define QUP7_BASE ((uint32_t)GSBI_QUP7_BASE)
+
+#define GSBI5_QUP5_REG_BASE (QUP5_BASE + 0x00000000)
+#define GSBI6_QUP6_REG_BASE (QUP6_BASE + 0x00000000)
+#define GSBI7_QUP7_REG_BASE (QUP7_BASE + 0x00000000)
+
+#define GSBI5_REG_BASE ((uint32_t)(GSBI5_BASE + 0x00000000))
+#define GSBI6_REG_BASE ((uint32_t)(GSBI6_BASE + 0x00000000))
+#define GSBI7_REG_BASE ((uint32_t)(GSBI7_BASE + 0x00000000))
+
+#define BOOT_SPI_PORT5_BASE QUP5_BASE
+#define BOOT_SPI_PORT6_BASE QUP6_BASE
+#define BOOT_SPI_PORT7_BASE QUP7_BASE
+
+#define GSBI5_SPI_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000300)
+#define GSBI6_SPI_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000300)
+#define GSBI7_SPI_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000300)
+
+#define GSBI5_SPI_IO_CONTROL_REG (GSBI5_QUP5_REG_BASE + 0x00000304)
+#define GSBI6_SPI_IO_CONTROL_REG (GSBI6_QUP6_REG_BASE + 0x00000304)
+#define GSBI7_SPI_IO_CONTROL_REG (GSBI7_QUP7_REG_BASE + 0x00000304)
+
+#define GSBI5_SPI_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x00000308)
+#define GSBI6_SPI_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x00000308)
+#define GSBI7_SPI_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x00000308)
+
+#define GSBI5_SPI_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x0000030c)
+#define GSBI6_SPI_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x0000030c)
+#define GSBI7_SPI_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x0000030c)
+
+#define GSBI5_GSBI_CTRL_REG_REG (GSBI5_REG_BASE + 0x00000000)
+#define GSBI6_GSBI_CTRL_REG_REG (GSBI6_REG_BASE + 0x00000000)
+#define GSBI7_GSBI_CTRL_REG_REG (GSBI7_REG_BASE + 0x00000000)
+
+#define GSBI5_QUP_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000000)
+#define GSBI6_QUP_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000000)
+#define GSBI7_QUP_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000000)
+
+#define GSBI5_QUP_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x0000001c)
+#define GSBI6_QUP_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x0000001c)
+#define GSBI7_QUP_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x0000001c)
+
+#define GSBI5_QUP_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x00000020)
+#define GSBI6_QUP_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x00000020)
+#define GSBI7_QUP_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x00000020)
+
+#define GSBI5_QUP_OPERATIONAL_REG (GSBI5_QUP5_REG_BASE + 0x00000018)
+#define GSBI6_QUP_OPERATIONAL_REG (GSBI6_QUP6_REG_BASE + 0x00000018)
+#define GSBI7_QUP_OPERATIONAL_REG (GSBI7_QUP7_REG_BASE + 0x00000018)
+
+#define GSBI5_QUP_IO_MODES_REG (GSBI5_QUP5_REG_BASE + 0x00000008)
+#define GSBI6_QUP_IO_MODES_REG (GSBI6_QUP6_REG_BASE + 0x00000008)
+#define GSBI7_QUP_IO_MODES_REG (GSBI7_QUP7_REG_BASE + 0x00000008)
+
+#define GSBI5_QUP_STATE_REG (GSBI5_QUP5_REG_BASE + 0x00000004)
+#define GSBI6_QUP_STATE_REG (GSBI6_QUP6_REG_BASE + 0x00000004)
+#define GSBI7_QUP_STATE_REG (GSBI7_QUP7_REG_BASE + 0x00000004)
+
+#define GSBI5_QUP_OUT_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x0000010c)
+#define GSBI6_QUP_OUT_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x0000010c)
+#define GSBI7_QUP_OUT_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x0000010c)
+
+#define GSBI5_QUP_IN_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x00000214)
+#define GSBI6_QUP_IN_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x00000214)
+#define GSBI7_QUP_IN_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x00000214)
+
+#define GSBI5_QUP_INPUT_FIFOc_REG(c) \
+ (GSBI5_QUP5_REG_BASE + 0x00000218 + 4 * (c))
+#define GSBI6_QUP_INPUT_FIFOc_REG(c) \
+ (GSBI6_QUP6_REG_BASE + 0x00000218 + 4 * (c))
+#define GSBI7_QUP_INPUT_FIFOc_REG(c) \
+ (GSBI7_QUP7_REG_BASE + 0x00000218 + 4 * (c))
+
+#define GSBI5_QUP_OUTPUT_FIFOc_REG(c) \
+ (GSBI5_QUP5_REG_BASE + 0x00000110 + 4 * (c))
+#define GSBI6_QUP_OUTPUT_FIFOc_REG(c) \
+ (GSBI6_QUP6_REG_BASE + 0x00000110 + 4 * (c))
+#define GSBI7_QUP_OUTPUT_FIFOc_REG(c) \
+ (GSBI7_QUP7_REG_BASE + 0x00000110 + 4 * (c))
+
+#define GSBI5_QUP_MX_INPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000200)
+#define GSBI6_QUP_MX_INPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000200)
+#define GSBI7_QUP_MX_INPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000200)
+
+#define GSBI5_QUP_MX_OUTPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000100)
+#define GSBI6_QUP_MX_OUTPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000100)
+#define GSBI7_QUP_MX_OUTPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000100)
+
+#define GSBI5_QUP_SW_RESET_REG (GSBI5_QUP5_REG_BASE + 0x0000000c)
+#define GSBI6_QUP_SW_RESET_REG (GSBI6_QUP6_REG_BASE + 0x0000000c)
+#define GSBI7_QUP_SW_RESET_REG (GSBI7_QUP7_REG_BASE + 0x0000000c)
+
+#define CLK_CTL_REG_BASE 0x00900000
+#define GSBIn_RESET_REG(n) \
+ (CLK_CTL_REG_BASE + 0x000029dc + 32 * ((n)-1))
+
+#define SFAB_AHB_S3_FCLK_CTL_REG \
+ (CLK_CTL_REG_BASE + 0x0000216c)
+#define CFPB_CLK_NS_REG \
+ (CLK_CTL_REG_BASE + 0x0000264c)
+#define SFAB_CFPB_S_HCLK_CTL_REG \
+ (CLK_CTL_REG_BASE + 0x000026c0)
+#define CFPB_SPLITTER_HCLK_CTL_REG \
+ (CLK_CTL_REG_BASE + 0x000026e0)
+#define CFPB0_HCLK_CTL_REG \
+ (CLK_CTL_REG_BASE + 0x00002650)
+#define CFPB2_HCLK_CTL_REG \
+ (CLK_CTL_REG_BASE + 0x00002658)
+#define GSBIn_HCLK_CTL_REG(n) \
+ (CLK_CTL_REG_BASE + 0x000029c0 + 32 * ((n)-1))
+#define GSBIn_QUP_APPS_NS_REG(n) \
+ (CLK_CTL_REG_BASE + 0x000029cc + 32 * ((n)-1))
+#define GSBIn_QUP_APPS_MD_REG(n) \
+ (CLK_CTL_REG_BASE + 0x000029c8 + 32 * ((n)-1))
+#define CLK_HALT_CFPB_STATEB_REG \
+ (CLK_CTL_REG_BASE + 0x00002fd0)
+
+#define GSBI5_HCLK 23
+#define GSBI6_HCLK 19
+#define GSBI7_HCLK 15
+#define GSBI5_QUP_APPS_CLK 20
+#define GSBI6_QUP_APPS_CLK 16
+#define GSBI7_QUP_APPS_CLK 12
+#define GSBI_CLK_BRANCH_ENA_MSK (1 << 4)
+#define GSBI_CLK_BRANCH_ENA (1 << 4)
+#define GSBI_CLK_BRANCH_DIS (0 << 4)
+#define QUP_CLK_BRANCH_ENA_MSK (1 << 9)
+#define QUP_CLK_BRANCH_ENA (1 << 9)
+#define QUP_CLK_BRANCH_DIS (0 << 9)
+#define CLK_ROOT_ENA_MSK (1 << 11)
+#define CLK_ROOT_ENA (1 << 11)
+#define CLK_ROOT_DIS (0 << 11)
+
+#define QUP_STATE_VALID_BIT 2
+#define QUP_STATE_VALID 1
+#define QUP_STATE_MASK 0x3
+#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8)
+#define QUP_CONFIG_MINI_CORE_SPI (1 << 8)
+#define SPI_QUP_CONF_INPUT_MSK (1 << 7)
+#define SPI_QUP_CONF_INPUT_ENA (0 << 7)
+#define SPI_QUP_CONF_NO_INPUT (1 << 7)
+#define SPI_QUP_CONF_OUTPUT_MSK (1 << 6)
+#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6)
+#define SPI_QUP_CONF_NO_OUTPUT (1 << 6)
+#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6)
+#define QUP_STATE_RESET_STATE 0x0
+#define QUP_STATE_RUN_STATE 0x1
+#define QUP_STATE_PAUSE_STATE 0x3
+#define SPI_BIT_WORD_MSK 0x1F
+#define SPI_8_BIT_WORD 0x07
+#define PROTOCOL_CODE_MSK (0x07 << 4)
+#define PROTOCOL_CODE_SPI (0x03 << 4)
+#define LOOP_BACK_MSK (1 << 8)
+#define NO_LOOP_BACK (0 << 8)
+#define SLAVE_OPERATION_MSK (1 << 5)
+#define SLAVE_OPERATION (0 << 5)
+#define CLK_ALWAYS_ON (0 << 9)
+#define MX_CS_MODE (0 << 8)
+#define NO_TRI_STATE (1 << 0)
+#define OUTPUT_BIT_SHIFT_MSK (1 << 16)
+#define OUTPUT_BIT_SHIFT_EN (1 << 16)
+#define INPUT_BLOCK_MODE_MSK (0x03 << 12)
+#define INPUT_BLOCK_MODE (0x01 << 12)
+#define OUTPUT_BLOCK_MODE_MSK (0x03 << 10)
+#define OUTPUT_BLOCK_MODE (0x01 << 10)
+#define GSBI1_RESET (1 << 0)
+#define GSBI1_RESET_MSK 0x1
+
+#define GSBI_M_VAL_SHFT 16
+#define GSBIn_M_VAL_MSK (0xFF << GSBI_M_VAL_SHFT)
+#define GSBI_N_VAL_SHFT 16
+#define GSBIn_N_VAL_MSK (0xFF << GSBI_N_VAL_SHFT)
+#define GSBI_D_VAL_SHFT 0
+#define GSBIn_D_VAL_MSK (0xFF << GSBI_D_VAL_SHFT)
+#define MNCNTR_RST_MSK (1 << 7)
+#define MNCNTR_RST_ENA (1 << 7)
+#define MNCNTR_RST_DIS (0 << 7)
+#define MNCNTR_MSK (1 << 8)
+#define MNCNTR_EN (1 << 8)
+#define MNCNTR_DIS (0 << 8)
+#define MNCNTR_MODE_MSK (0x3 << 5)
+#define MNCNTR_MODE_BYPASS (0 << 5)
+#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5)
+#define GSBI_PRE_DIV_SEL_SHFT 3
+#define GSBIn_PRE_DIV_SEL_MSK (0x3 << GSBI_PRE_DIV_SEL_SHFT)
+#define GSBIn_PLL_SRC_MSK (0x03 << 0)
+#define GSBIn_PLL_SRC_PXO (0 << 0)
+#define GSBIn_PLL_SRC_PLL8 (0x3 << 0)
+
+#define SPI_INPUT_FIRST_MODE (1 << 9)
+#define SPI_IO_CONTROL_CLOCK_IDLE_HIGH (1 << 10)
+#define QUP_DATA_AVAILABLE_FOR_READ (1 << 5)
+#define QUP_OUTPUT_FIFO_NOT_EMPTY (1 << 4)
+#define OUTPUT_SERVICE_FLAG (1 << 8)
+#define INPUT_SERVICE_FLAG (1 << 9)
+#define QUP_OUTPUT_FIFO_FULL (1 << 6)
+#define QUP_INPUT_FIFO_NOT_EMPTY (1 << 5)
+#define SPI_INPUT_BLOCK_SIZE 4
+#define SPI_OUTPUT_BLOCK_SIZE 4
+#define GSBI5_SPI_CLK 21
+#define GSBI5_SPI_MISO 19
+#define GSBI5_SPI_MOSI 18
+#define GSBI5_SPI_CS_0 20
+#define GSBI5_SPI_CS_1 61
+#define GSBI5_SPI_CS_2 62
+#define GSBI5_SPI_CS_3 2
+#define GSBI6_SPI_CLK 30
+#define GSBI6_SPI_CS_0 29
+#define GSBI6_SPI_MISO 28
+#define GSBI6_SPI_MOSI 27
+#define GSBI7_SPI_CLK 9
+#define GSBI7_SPI_CS_0 8
+#define GSBI7_SPI_MISO 7
+#define GSBI7_SPI_MOSI 6
+
+#define MSM_GSBI_MAX_FREQ 51200000
+
+#define SPI_RESET_STATE 0
+#define SPI_RUN_STATE 1
+#define SPI_PAUSE_STATE 3
+#define SPI_CORE_RESET 0
+#define SPI_CORE_RUNNING 1
+#define GSBI_SPI_MODE_0 0
+#define GSBI_SPI_MODE_1 1
+#define GSBI_SPI_MODE_2 2
+#define GSBI_SPI_MODE_3 3
+#define GSBI5_SPI 0
+#define GSBI6_SPI 1
+#define GSBI7_SPI 2
+
+struct gsbi_spi {
+ unsigned int spi_config;
+ unsigned int io_control;
+ unsigned int error_flags;
+ unsigned int error_flags_en;
+ unsigned int gsbi_ctrl;
+ unsigned int qup_config;
+ unsigned int qup_error_flags;
+ unsigned int qup_error_flags_en;
+ unsigned int qup_operational;
+ unsigned int qup_io_modes;
+ unsigned int qup_state;
+ unsigned int qup_input_fifo;
+ unsigned int qup_output_fifo;
+ unsigned int qup_mx_input_count;
+ unsigned int qup_mx_output_count;
+ unsigned int qup_sw_reset;
+ unsigned int qup_ns_reg;
+ unsigned int qup_md_reg;
+};
+
+struct ipq_spi_slave {
+ struct spi_slave slave;
+ const struct gsbi_spi *regs;
+ unsigned int mode;
+ unsigned int initialized;
+ unsigned long freq;
+ int allocated;
+};
+
+static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct ipq_spi_slave, slave);
+}
+
+#endif /* _IPQ40XX_SPI_H_ */
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/usb.h b/src/soc/qualcomm/ipq40xx/include/soc/usb.h
new file mode 100644
index 0000000000..457ead7ec1
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/usb.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _IPQ40XX_USB_H_
+#define _IPQ40XX_USB_H_
+
+void setup_usb_host1(void);
+void setup_usb_host2(void);
+
+#endif /* _IPQ40XX_USB_H_ */
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h b/src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h
new file mode 100644
index 0000000000..134b63f19c
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_USBL_IF_H__
+#define __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_USBL_IF_H__
+
+#include <types.h>
+
+typedef struct {
+ u32 time_stamp;
+ char msg[27];
+ u8 type;
+
+} boot_log_entry;
+
+typedef struct {
+ u32 num_log_entries;
+ boot_log_entry *log;
+} sbl_ro_info;
+
+typedef struct {
+ u32 start_magic;
+ u32 num;
+ char *version;
+ sbl_ro_info info[2];
+ /*
+ * The two addresses below can be used for communicating with the RPM
+ * (passing it the starting address of the program to execute and
+ * triggering the jump to the program). Presently these addresses are
+ * hardcodeded in firmware source code.
+ */
+ u32 *rpm_jump_trigger;
+ u32 *rpm_entry_addr_ptr;
+ u32 end_magic;
+} uber_sbl_shared_info;
+
+#define UBER_SBL_SHARED_INFO_START_MAGIC 0x5552504d // URPM
+#define UBER_SBL_SHARED_INFO_END_MAGIC 0x554b5254 // UKRT
+
+extern uber_sbl_shared_info *maskrom_param;
+
+#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-06 03:11:03 +0000