soc/qualcomm/ipq40xx: Enable timer

BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Original-Commit-Id: 35c0e6046899dc1af03736ae9fa77f9eeec7f668
Original-Change-Id: I681e92fa673c1d3aee2974a7bba5074e2bfd6e02
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333297
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

squashed:

soc/qualcomm/ipq40xx: Enable UART on ipq40xx

- BLSP/UART Clock configuration
- GPIO Configuration

BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Original-Commit-Id: 7bba1fc7f50e7aeb4e7b37f164e85771e53f47e6
Original-Change-Id: I474a0e97b24ac9b3f2cba599cd709b6801b08f91
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333300
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I5e31d036ee7ddcf72ed9739cef1f7f7d0ca6c427
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14667
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

4 files changed, 67 insertions, 55 deletions

diff --git a/src/soc/qualcomm/ipq40xx/include/soc/clock.h b/src/soc/qualcomm/ipq40xx/include/soc/clock.h
index 51cc228c71..89343f0168 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/clock.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/clock.h
@@ -34,7 +34,7 @@
 #include <soc/iomap.h>
 
 /* UART clock @ 7.3728 MHz */
-#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
 
 /* UART specific definitions */
 
@@ -205,8 +205,8 @@
 /* Uart specific clock settings */
 
 void uart_pll_vote_clk_enable(unsigned int);
-void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n,
-		unsigned int d, unsigned int clk_dummy);
+void uart_clock_config(unsigned int blsp_uart, unsigned int m, unsigned int n,
+		unsigned int d);
 void nand_clock_config(void);
 void usb_clock_config(void);
 int audio_clock_config(unsigned frequency);
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h
index 6304f71757..56aef77829 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h
@@ -69,16 +69,22 @@
 #define GPIO_MAX_NUM  68
 
 /* GPIO TLMM: Mask */
-#define GPIO_CFG_PULL_MASK    0x3
-#define GPIO_CFG_FUNC_MASK    0xF
-#define GPIO_CFG_DRV_MASK     0x7
-#define GPIO_CFG_OE_MASK      0x1
+#define GPIO_CFG_PULL_MASK	0x3
+#define GPIO_CFG_FUNC_MASK	0xF
+#define GPIO_CFG_DRV_MASK	0x7
+#define GPIO_CFG_OE_MASK	0x1
+#define GPIO_CFG_VM_MASK	0x1
+#define GPIO_CFG_OD_EN_MASK	0x1
+#define GPIO_CFG_PU_REMASKFT	0x3
 
 /* GPIO TLMM: Shift */
-#define GPIO_CFG_PULL_SHIFT   0
-#define GPIO_CFG_FUNC_SHIFT   2
-#define GPIO_CFG_DRV_SHIFT    6
-#define GPIO_CFG_OE_SHIFT     9
+#define GPIO_CFG_PULL_SHIFT	0
+#define GPIO_CFG_FUNC_SHIFT	2
+#define GPIO_CFG_DRV_SHIFT	6
+#define GPIO_CFG_OE_SHIFT	9
+#define GPIO_CFG_VM_SHIFT	11
+#define GPIO_CFG_OD_EN_SHIFT	12
+#define GPIO_CFG_PU_RES_SHIFT	13
 
 /* GPIO IO: Mask */
 #define GPIO_IO_IN_MASK       0x1
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
index 543356dcbc..0f3c6a5cfa 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
@@ -49,37 +49,36 @@
 #define clrsetbits_le32_i(addr, clear, set)  \
 	clrsetbits_le32(((void *)(addr)), (clear), (set))
 
-#define MSM_CLK_CTL_BASE    ((void *)0x00900000)
-
-#define MSM_TMR_BASE        ((void *)0x0200A000)
-#define MSM_GPT_BASE        (MSM_TMR_BASE + 0x04)
-#define MSM_DGT_BASE        (MSM_TMR_BASE + 0x24)
-
-#define GPT_REG(off)        (MSM_GPT_BASE + (off))
-#define DGT_REG(off)        (MSM_DGT_BASE + (off))
-
-#define APCS_WDT0_EN        (MSM_TMR_BASE + 0x0040)
-#define APCS_WDT0_RST       (MSM_TMR_BASE + 0x0038)
-#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C)
-#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C)
-
-#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820)
-
-#define GPT_MATCH_VAL        GPT_REG(0x0000)
-#define GPT_COUNT_VAL        GPT_REG(0x0004)
-#define GPT_ENABLE           GPT_REG(0x0008)
-#define GPT_CLEAR            GPT_REG(0x000C)
-
-#define GPT1_MATCH_VAL       GPT_REG(0x00010)
-#define GPT1_COUNT_VAL       GPT_REG(0x00014)
-#define GPT1_ENABLE          GPT_REG(0x00018)
-#define GPT1_CLEAR           GPT_REG(0x0001C)
-
-#define DGT_MATCH_VAL        DGT_REG(0x0000)
-#define DGT_COUNT_VAL        DGT_REG(0x0004)
-#define DGT_ENABLE           DGT_REG(0x0008)
-#define DGT_CLEAR            DGT_REG(0x000C)
-#define DGT_CLK_CTL          DGT_REG(0x0010)
+#define GCC_CLK_CTL_REG			((void *)0x01800000u)
+#define MSM_CLK_CTL_BASE		GCC_CLK_CTL_REG
+#define GCC_CLK_BRANCH_ENA		(GCC_CLK_CTL_REG + 0x6000)
+#define		IMEM_AXI		(1 << 17)
+#define		SYS_NOC_APSS_AHB	(1 << 16)
+#define		BIMC_AXI_M0		(1 << 15)
+#define		APSS_AHB		(1 << 14)
+#define		APSS_AXI		(1 << 13)
+#define		MPM_AHB			(1 << 12)
+#define		GMEM_SYS_NOC_AXI	(1 << 11)
+#define		BLSP1_AHB		(1 << 10)
+#define		BLSP1_SLEEP		(1 << 9)
+#define		PRNG_AHB		(1 << 8)
+#define		BOOT_ROM_AHB		(1 << 7)
+#define		MSG_RAM_AHB		(1 << 6)
+#define		TLMM_AHB		(1 << 5)
+#define		TLMM			(1 << 4)
+#define		SPMI_PCNOC_AHB		(1 << 3)
+#define		CRYPTO			(1 << 2)
+#define		CRYPTO_AXI		(1 << 1)
+#define		CRYPTO_AHB		(1 << 0)
+
+#define GCNT_GLOBAL_CTRL_BASE	((void *)0x004a0000u)
+#define GCNT_CNTCR		(GCNT_GLOBAL_CTRL_BASE + 0x1000)
+#define GCNT_GLB_CNTCV_LO	(GCNT_GLOBAL_CTRL_BASE + 0x1008)
+#define GCNT_GLB_CNTCV_HI	(GCNT_GLOBAL_CTRL_BASE + 0x100c)
+#define GCNT_CNTCV_LO		(GCNT_GLOBAL_CTRL_BASE + 0x2000)
+#define GCNT_CNTCV_HI		(GCNT_GLOBAL_CTRL_BASE + 0x2004)
+
+#define GCNT_PSHOLD		((void *)0x004AB000u)
 
 /* RPM interface constants */
 #define RPM_INT           ((void *)0x63020)
@@ -88,8 +87,8 @@
 #define RPM_SIGNAL_ENTRY  ((void *)0x47C24)
 #define RPM_FW_MAGIC_NUM 0x4D505242
 
-#define TLMM_BASE_ADDR      ((void *)0x00800000)
-#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define TLMM_BASE_ADDR      ((void *)0x01000000)
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x))
 #define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4)
 
 /* Yes, this is not a typo... host2 is actually mapped before host1. */
@@ -100,16 +99,23 @@
 #define USB_HOST1_DWC3_BASE	0x1100C100
 #define USB_HOST1_PHY_BASE	0x110F8800
 
-#define GSBI_4			4
-#define UART1_DM_BASE         	0x12450000
-#define UART_GSBI1_BASE       	0x12440000
-#define UART2_DM_BASE		0x12490000
-#define UART_GSBI2_BASE		0x12480000
-#define UART4_DM_BASE         	0x16340000
-#define UART_GSBI4_BASE       	0x16300000
-
-#define UART2_DM_BASE           0x12490000
-#define UART_GSBI2_BASE         0x12480000
+#define UART1_DM_BASE		((void *)0x078af000)
+#define UART2_DM_BASE		((void *)0x078b0000)
+
+enum {
+	BLSP1_UART1,
+	BLSP1_UART2,
+};
+
+#define GCC_BLSP1_UART_BCR_BASE		(GCC_CLK_CTL_REG + 0x2038)
+#define GCC_BLSP1_UART_BCR(x)		(GCC_BLSP1_UART_BCR_BASE + (x) * 0xff0)
+#define GCC_BLSP1_UART_APPS_CBCR(x)	(GCC_BLSP1_UART_BCR(x) + 4)
+#define GCC_BLSP1_UART_APPS_CMD_RCGR(x)	(GCC_BLSP1_UART_APPS_CBCR(x) + 8)
+#define GCC_BLSP1_UART_APPS_CFG_RCGR(x)	(GCC_BLSP1_UART_APPS_CMD_RCGR(x) + 4)
+#define GCC_BLSP1_UART_APPS_M(x)	(GCC_BLSP1_UART_APPS_CFG_RCGR(x) + 4)
+#define GCC_BLSP1_UART_APPS_N(x)	(GCC_BLSP1_UART_APPS_M(x) + 4)
+#define GCC_BLSP1_UART_APPS_D(x)	(GCC_BLSP1_UART_APPS_N(x) + 4)
+#define GCC_BLSP1_UART_MISC(x)		(GCC_BLSP1_UART_APPS_D(x) + 4)
 
 #define GSBI1_BASE		((void *)0x12440000)
 #define GSBI2_BASE		((void *)0x12480000)
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h b/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h
index 25a06bff93..8cb0f25a8c 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h
@@ -30,7 +30,7 @@
 #ifndef __UART_DM_H__
 #define __UART_DM_H__
 
-#define PERIPH_BLK_BLSP 0
+#define PERIPH_BLK_BLSP 1
 
 #define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
 	((value << (32 - end_pos)) >> (32 - (end_pos - start_pos)))