soc/qualcomm/ipq40xx: Add support for BLSP QUP I2C

Able to talk to the TPM device and the commands
seem to succeed.

BUG=chrome-os-partner:49249 chrome-os-partner:49250
TEST=All commands to the TPM succeed
BRANCH=none

Original-Commit-Id: c13900108f524c8422c38dee88469c8bfe24d0bd
Original-Change-Id: Ie8c3c1ab1290cd8d7e6ddd1ae22f765c7be81019
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333314
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

squashed:

soc/qualcomm/ipq40xx: Add support for BLSP QUP SPI

- Enable BLSP SPI driver for ipq40xx
- supports only FIFO mode

BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Original-Commit-Id: 0714025975854dd048d35fe602824ead4c7d94e9
Original-Change-Id: If809b0fdf7d6c9405db6fd3747a3774c00ea9870
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333303
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ia518af5bfc782b08a0883ac93224d476d07e2426
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

6 files changed, 233 insertions, 361 deletions

diff --git a/src/soc/qualcomm/ipq40xx/include/soc/gsbi.h b/src/soc/qualcomm/ipq40xx/include/soc/blsp.h
index f2c375df0f..ce74e56dcc 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/gsbi.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/blsp.h
@@ -28,48 +28,33 @@
  */
 
 
-#ifndef __GSBI_H_
-#define __GSBI_H_
-
-/* GSBI Registers */
-#define GSBI_CTRL_REG(base)        ((base) + 0x0)
-
-#define GSBI_CTRL_REG_PROTOCOL_CODE_S   4
-#define GSBI_PROTOCOL_CODE_I2C          0x2
-#define GSBI_PROTOCOL_CODE_SPI          0x3
-#define GSBI_PROTOCOL_CODE_UART_FLOW    0x4
-#define GSBI_PROTOCOL_CODE_I2C_UART     0x6
-
-#define GSBI_HCLK_CTL_S                 4
-#define GSBI_HCLK_CTL_CLK_ENA           0x1
+#ifndef __BLSP_H_
+#define __BLSP_H_
 
 typedef enum {
-	GSBI_ID_1 = 1,
-	GSBI_ID_2,
-	GSBI_ID_3,
-	GSBI_ID_4,
-	GSBI_ID_5,
-	GSBI_ID_6,
-	GSBI_ID_7,
-} gsbi_id_t;
+	BLSP_QUP_ID_0,
+	BLSP_QUP_ID_1,
+	BLSP_QUP_ID_2,
+	BLSP_QUP_ID_3,
+} blsp_qup_id_t;
 
 typedef enum {
-	GSBI_SUCCESS = 0,
-	GSBI_ID_ERROR,
-	GSBI_ERROR,
-	GSBI_UNSUPPORTED
-} gsbi_return_t;
+	BLSP_SUCCESS = 0,
+	BLSP_ID_ERROR,
+	BLSP_ERROR,
+	BLSP_UNSUPPORTED
+} blsp_return_t;
 
 typedef enum {
-	GSBI_PROTO_I2C_UIM = 1,
-	GSBI_PROTO_I2C_ONLY,
-	GSBI_PROTO_SPI_ONLY,
-	GSBI_PROTO_UART_FLOW_CTL,
-	GSBI_PROTO_UIM,
-	GSBI_PROTO_I2C_UART,
-} gsbi_protocol_t;
-
-gsbi_return_t gsbi_init(gsbi_id_t gsbi_id, gsbi_protocol_t protocol);
-int gsbi_init_board(gsbi_id_t gsbi_id);
+	BLSP_PROTO_I2C_UIM = 1,
+	BLSP_PROTO_I2C_ONLY,
+	BLSP_PROTO_SPI_ONLY,
+	BLSP_PROTO_UART_FLOW_CTL,
+	BLSP_PROTO_UIM,
+	BLSP_PROTO_I2C_UART,
+} blsp_protocol_t;
+
+blsp_return_t blsp_i2c_init(blsp_qup_id_t id);
+int blsp_i2c_init_board(blsp_qup_id_t id);
 
 #endif
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/clock.h b/src/soc/qualcomm/ipq40xx/include/soc/clock.h
index 89343f0168..8544c4382d 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/clock.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/clock.h
@@ -210,5 +210,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m, unsigned int n,
 void nand_clock_config(void);
 void usb_clock_config(void);
 int audio_clock_config(unsigned frequency);
+int blsp_i2c_clock_config(blsp_qup_id_t id);
+
 
 #endif  /*  __PLATFORM_IPQ40XX_CLOCK_H_ */
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h
index 56aef77829..d4ff32697f 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h
@@ -113,4 +113,7 @@ static inline void gpio_tlmm_config(unsigned int gpio, unsigned int func,
 {
 	gpio_tlmm_config_set(gpio, func, pull, drvstr, enable);
 }
+
+void ipq_setup_tpm(void);
+
 #endif // __SOC_QUALCOMM_IPQ40XX_GPIO_H_
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
index 0f3c6a5cfa..bfdfb56f8e 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
@@ -38,6 +38,7 @@
 
 #include <arch/io.h>
 #include <soc/cdp.h>
+#include <soc/blsp.h>
 
 /* Typecast to allow integers being passed as address
    This needs to be included because vendor code is not compliant with our
@@ -71,6 +72,13 @@
 #define		CRYPTO_AXI		(1 << 1)
 #define		CRYPTO_AHB		(1 << 0)
 
+#define GCC_BLSP1_QUP1_I2C_APPS_CBCR		(MSM_CLK_CTL_BASE + 0x2008)
+#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR	(MSM_CLK_CTL_BASE + 0x200c)
+#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR	(MSM_CLK_CTL_BASE + 0x2010)
+#define GCC_BLSP1_QUP2_I2C_APPS_CBCR		(MSM_CLK_CTL_BASE + 0x3010)
+#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR	(MSM_CLK_CTL_BASE + 0x3000)
+#define GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR	(MSM_CLK_CTL_BASE + 0x3004)
+
 #define GCNT_GLOBAL_CTRL_BASE	((void *)0x004a0000u)
 #define GCNT_CNTCR		(GCNT_GLOBAL_CTRL_BASE + 0x1000)
 #define GCNT_GLB_CNTCV_LO	(GCNT_GLOBAL_CTRL_BASE + 0x1008)
@@ -117,55 +125,28 @@ enum {
 #define GCC_BLSP1_UART_APPS_D(x)	(GCC_BLSP1_UART_APPS_N(x) + 4)
 #define GCC_BLSP1_UART_MISC(x)		(GCC_BLSP1_UART_APPS_D(x) + 4)
 
-#define GSBI1_BASE		((void *)0x12440000)
-#define GSBI2_BASE		((void *)0x12480000)
-#define GSBI3_BASE		((void *)0x16200000)
-#define GSBI4_BASE		((void *)0x16300000)
-#define GSBI5_BASE		((void *)0x1A200000)
-#define GSBI6_BASE		((void *)0x16500000)
-#define GSBI7_BASE		((void *)0x16600000)
-
-#define GSBI1_CTL_REG		(GSBI1_BASE + (0x0))
-#define GSBI2_CTL_REG		(GSBI2_BASE + (0x0))
-#define GSBI3_CTL_REG		(GSBI3_BASE + (0x0))
-#define GSBI4_CTL_REG		(GSBI4_BASE + (0x0))
-#define GSBI5_CTL_REG		(GSBI5_BASE + (0x0))
-#define GSBI6_CTL_REG		(GSBI6_BASE + (0x0))
-#define GSBI7_CTL_REG		(GSBI7_BASE + (0x0))
-
-#define GSBI_QUP1_BASE		(GSBI1_BASE + 0x20000)
-#define GSBI_QUP2_BASE		(GSBI2_BASE + 0x20000)
-#define GSBI_QUP3_BASE		(GSBI3_BASE + 0x80000)
-#define GSBI_QUP4_BASE		(GSBI4_BASE + 0x80000)
-#define GSBI_QUP5_BASE		(GSBI5_BASE + 0x80000)
-#define GSBI_QUP6_BASE		(GSBI6_BASE + 0x80000)
-#define GSBI_QUP7_BASE		(GSBI7_BASE + 0x80000)
-
-#define GSBI_CTL_PROTO_I2C              2
-#define GSBI_CTL_PROTO_CODE_SFT         4
-#define GSBI_CTL_PROTO_CODE_MSK         0x7
-#define GSBI_HCLK_CTL_GATE_ENA          6
-#define GSBI_HCLK_CTL_BRANCH_ENA        4
-#define GSBI_QUP_APPS_M_SHFT            16
-#define GSBI_QUP_APPS_M_MASK            0xFF
-#define GSBI_QUP_APPS_D_SHFT            0
-#define GSBI_QUP_APPS_D_MASK            0xFF
-#define GSBI_QUP_APPS_N_SHFT            16
-#define GSBI_QUP_APPS_N_MASK            0xFF
-#define GSBI_QUP_APPS_ROOT_ENA_SFT      11
-#define GSBI_QUP_APPS_BRANCH_ENA_SFT    9
-#define GSBI_QUP_APPS_MNCTR_EN_SFT      8
-#define GSBI_QUP_APPS_MNCTR_MODE_MSK    0x3
-#define GSBI_QUP_APPS_MNCTR_MODE_SFT    5
-#define GSBI_QUP_APPS_PRE_DIV_MSK       0x3
-#define GSBI_QUP_APPS_PRE_DIV_SFT       3
-#define GSBI_QUP_APPS_SRC_SEL_MSK       0x7
-
-
-#define GSBI_QUP_APSS_MD_REG(gsbi_n)	((MSM_CLK_CTL_BASE + 0x29c8) + \
-							(32*(gsbi_n-1)))
-#define GSBI_QUP_APSS_NS_REG(gsbi_n)	((MSM_CLK_CTL_BASE + 0x29cc) + \
-							(32*(gsbi_n-1)))
-#define GSBI_HCLK_CTL(n)		((MSM_CLK_CTL_BASE + 0x29C0) + \
-							(32*(n-1)))
+#define BLSP1_QUP0_BASE		((void *)0x078B5000)
+#define BLSP1_QUP1_BASE		((void *)0x078B6000)
+#define BLSP1_QUP2_BASE		((void *)0x078B7000)
+#define BLSP1_QUP3_BASE		((void *)0x078B8000)
+
+static inline void *blsp_qup_base(blsp_qup_id_t id)
+{
+	switch (id) {
+	case BLSP_QUP_ID_0: return BLSP1_QUP0_BASE;
+	case BLSP_QUP_ID_1: return BLSP1_QUP1_BASE;
+	case BLSP_QUP_ID_2: return BLSP1_QUP2_BASE;
+	case BLSP_QUP_ID_3: return BLSP1_QUP3_BASE;
+	}
+	return NULL;
+}
+
+#define BLSP_MINI_CORE_SHIFT		8
+#define BLSP_MINI_CORE_I2C		(0x2u << BLSP_MINI_CORE_SHIFT)
+#define BLSP_MINI_CORE_MASK		(0xfu << BLSP_MINI_CORE_SHIFT)
+
+#define ETIMEDOUT -10
+#define EINVAL -11
+#define EIO -12
+
 #endif // __SOC_QUALCOMM_IPQ40XX_IOMAP_H_
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/qup.h b/src/soc/qualcomm/ipq40xx/include/soc/qup.h
index d0186f59b0..e55989a591 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/qup.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/qup.h
@@ -32,40 +32,50 @@
 #ifndef __QUP_H__
 #define __QUP_H__
 
-#include <soc/gsbi.h>
+#include <soc/blsp.h>
 
 /* QUP block registers */
-#define QUP_CONFIG			0x0
-#define QUP_STATE			0x4
-#define QUP_IO_MODES			0x8
-#define QUP_SW_RESET			0xc
-#define QUP_TIME_OUT			0x10
-#define QUP_TIME_OUT_CURRENT		0x14
-#define QUP_OPERATIONAL			0x18
-#define QUP_ERROR_FLAGS			0x1c
-#define QUP_ERROR_FLAGS_EN		0x20
-#define QUP_TEST_CTRL			0x24
+#define QUP_CONFIG			0x000
+#define QUP_STATE			0x004
+#define QUP_IO_MODES			0x008
+#define QUP_SW_RESET			0x00C
+#define QUP_TRANSFER_CANCEL		0x014
+#define QUP_OPERATIONAL			0x018
+#define QUP_ERROR_FLAGS			0x01C
+#define QUP_ERROR_FLAGS_EN		0x020
+#define QUP_TEST_CTRL			0x024
+#define QUP_OPERATIONAL_MASK		0x028
+#define QUP_HW_VERSION			0x030
 #define QUP_MX_OUTPUT_COUNT		0x100
 #define QUP_MX_OUTPUT_CNT_CURRENT	0x104
 #define QUP_OUTPUT_DEBUG		0x108
-#define QUP_OUTPUT_FIFO_WORD_CNT	0x10c
+#define QUP_OUTPUT_FIFO_WORD_CNT	0x10C
 #define QUP_OUTPUT_FIFO			0x110
+#define QUP_OUTPUT_FIFO_SIZE		64	/* bytes */
 #define QUP_MX_WRITE_COUNT		0x150
-#define QUP_WRITE_CNT_CURRENT		0x154
+#define QUP_MX_WRITE_CNT_CURRENT	0x154
 #define QUP_MX_INPUT_COUNT		0x200
-#define QUP_READ_COUNT			0x208
-#define QUP_MX_READ_CNT_CURRENT		0x20c
+#define QUP_MX_INPUT_CNT_CURRENT	0x204
+#define QUP_MX_READ_COUNT		0x208
+#define QUP_MX_READ_CNT_CURRENT		0x20C
 #define QUP_INPUT_DEBUG			0x210
 #define QUP_INPUT_FIFO_WORD_CNT		0x214
 #define QUP_INPUT_FIFO			0x218
+#define QUP_INPUT_FIFO_SIZE		64	/* bytes */
 #define QUP_I2C_MASTER_CLK_CTL		0x400
 #define QUP_I2C_MASTER_STATUS		0x404
+#define QUP_I2C_MASTER_CONFIG		0x408
+#define QUP_I2C_MASTER_BUS_CLEAR	0x40C
+#define QUP_I2C_MASTER_LOCAL_ID		0x410
+#define QUP_I2C_MASTER_COMMAND		0x414
 
 #define OUTPUT_FIFO_FULL		(1<<6)
 #define INPUT_FIFO_NOT_EMPTY		(1<<5)
 #define OUTPUT_FIFO_NOT_EMPTY		(1<<4)
 #define INPUT_SERVICE_FLAG		(1<<9)
 #define OUTPUT_SERVICE_FLAG		(1<<8)
+#define QUP_UNPACK_EN			(1<<14)
+#define QUP_PACK_EN			(1<<15)
 #define QUP_OUTPUT_BIT_SHIFT_EN		(1<<16)
 
 #define QUP_MODE_MASK			(0x03)
@@ -74,6 +84,8 @@
 
 #define QUP_FS_DIVIDER_MASK		(0xFF)
 
+#define QUP_APP_CLK_ON_EN		(1 << 12)
+#define QUP_CORE_CLK_ON_EN		(1 << 13)
 #define QUP_MINI_CORE_PROTO_SHFT	(8)
 #define QUP_MINI_CORE_PROTO_MASK	(0x0F)
 
@@ -170,50 +182,50 @@ typedef struct {
 } qup_data_t;
 
 /*
- * Initialize GSBI QUP block for FIFO I2C transfers.
- * gsbi_id[IN]: GSBI for which QUP is to be initialized.
+ * Initialize BLSP QUP block for FIFO I2C transfers.
+ * id[IN]: BLSP for which QUP is to be initialized.
  * config_ptr[IN]: configurations parameters for the QUP.
  *
  * return: QUP_SUCCESS, if initialization succeeds.
  */
-qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr);
+qup_return_t qup_init(blsp_qup_id_t id, const qup_config_t *config_ptr);
 
 /*
  * Set QUP state to run, pause, reset.
- * gsbi_id[IN]: GSBI block for which QUP state is to be set.
+ * id[IN]: BLSP block for which QUP state is to be set.
  * state[IN]: New state to transition to.
  *
  * return: QUP_SUCCESS, if state transition succeeds.
  */
-qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state);
+qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state);
 
 /*
  * Reset the status bits set during an i2c transfer.
- * gsbi_id[IN]: GSBI block for which i2c status bits are to be cleared.
+ * id[IN]: BLSP block for which i2c status bits are to be cleared.
  *
  * return: QUP_SUCCESS, if status bits are cleared successfully.
  */
-qup_return_t qup_reset_i2c_master_status(gsbi_id_t gsbi_id);
+qup_return_t qup_reset_i2c_master_status(blsp_qup_id_t id);
 
 /*
  * Send data to the peripheral on the bus.
- * gsbi_id[IN]: GSBI block for which data is to be sent.
+ * id[IN]: BLSP block for which data is to be sent.
  * p_tx_obj[IN]: Data to be sent to the slave on the bus.
  * stop_seq[IN]: When set to non-zero QUP engine sends i2c stop sequnce.
  *
  * return: QUP_SUCCESS, when data is sent successfully to the peripheral.
  */
-qup_return_t qup_send_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj,
+qup_return_t qup_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj,
 			   uint8_t stop_seq);
 
 /*
  * Receive data from peripheral on the bus.
- * gsbi_id[IN]: GSBI block from which data is to be received.
+ * id[IN]: BLSP block from which data is to be received.
  * p_tx_obj[IN]: length of data to be received, slave address.
  *      [OUT]: buffer filled with data from slave.
  *
  * return: QUP_SUCCESS, when data is received successfully.
  */
-qup_return_t qup_recv_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj);
+qup_return_t qup_recv_data(blsp_qup_id_t id, qup_data_t *p_tx_obj);
 
 #endif //__QUP_H__
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/spi.h b/src/soc/qualcomm/ipq40xx/include/soc/spi.h
index 8e52d62a01..014b333667 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/spi.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/spi.h
@@ -1,5 +1,5 @@
 /*
- * Register definitions for the IPQ GSBI Controller
+ * Register definitions for the IPQ BLSP SPI Controller
  *
  * Copyright (c) 2012 The Linux Foundation. All rights reserved.
  *
@@ -34,263 +34,152 @@
 
 #include <spi_flash.h>
 #include <soc/iomap.h>
+#include <soc/qup.h>
+
+#define BLSP0_QUP_REG_BASE		((void *)0x78b5000u)
+#define BLSP1_QUP_REG_BASE		((void *)0x78b6000u)
+
+#define BLSP0_SPI_CONFIG_REG		(BLSP0_QUP_REG_BASE + 0x00000300)
+#define BLSP1_SPI_CONFIG_REG		(BLSP1_QUP_REG_BASE + 0x00000300)
+
+#define BLSP0_SPI_IO_CONTROL_REG	(BLSP0_QUP_REG_BASE + 0x00000304)
+#define BLSP1_SPI_IO_CONTROL_REG	(BLSP1_QUP_REG_BASE + 0x00000304)
+
+#define BLSP0_SPI_ERROR_FLAGS_REG	(BLSP0_QUP_REG_BASE + 0x00000308)
+#define BLSP1_SPI_ERROR_FLAGS_REG	(BLSP1_QUP_REG_BASE + 0x00000308)
+
+#define BLSP0_SPI_DEASSERT_WAIT_REG	(BLSP0_QUP_REG_BASE + 0x00000310)
+#define BLSP1_SPI_DEASSERT_WAIT_REG	(BLSP1_QUP_REG_BASE + 0x00000310)
+#define BLSP0_SPI_ERROR_FLAGS_EN_REG	(BLSP0_QUP_REG_BASE + 0x0000030c)
+#define BLSP1_SPI_ERROR_FLAGS_EN_REG	(BLSP1_QUP_REG_BASE + 0x0000030c)
+
+#define BLSP0_QUP_CONFIG_REG		(BLSP0_QUP_REG_BASE + 0x00000000)
+#define BLSP1_QUP_CONFIG_REG		(BLSP1_QUP_REG_BASE + 0x00000000)
+
+#define BLSP0_QUP_ERROR_FLAGS_REG	(BLSP0_QUP_REG_BASE + 0x0000001c)
+#define BLSP1_QUP_ERROR_FLAGS_REG	(BLSP1_QUP_REG_BASE + 0x0000001c)
+
+#define BLSP0_QUP_ERROR_FLAGS_EN_REG	(BLSP0_QUP_REG_BASE + 0x00000020)
+#define BLSP1_QUP_ERROR_FLAGS_EN_REG	(BLSP1_QUP_REG_BASE + 0x00000020)
+
+#define BLSP0_QUP_OPERATIONAL_MASK	(BLSP0_QUP_REG_BASE + 0x00000028)
+#define BLSP1_QUP_OPERATIONAL_MASK	(BLSP1_QUP_REG_BASE + 0x00000028)
+
+#define BLSP0_QUP_OPERATIONAL_REG	(BLSP0_QUP_REG_BASE + 0x00000018)
+#define BLSP1_QUP_OPERATIONAL_REG	(BLSP1_QUP_REG_BASE + 0x00000018)
+
+#define BLSP0_QUP_IO_MODES_REG		(BLSP0_QUP_REG_BASE + 0x00000008)
+#define BLSP1_QUP_IO_MODES_REG		(BLSP1_QUP_REG_BASE + 0x00000008)
+
+#define BLSP0_QUP_STATE_REG		(BLSP0_QUP_REG_BASE + 0x00000004)
+#define BLSP1_QUP_STATE_REG		(BLSP1_QUP_REG_BASE + 0x00000004)
+
+#define BLSP0_QUP_INPUT_FIFOc_REG(c) \
+		(BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c))
+#define BLSP1_QUP_INPUT_FIFOc_REG(c) \
+		(BLSP1_QUP_REG_BASE + 0x00000218 + 4 * (c))
+
+#define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \
+		(BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c))
+#define BLSP1_QUP_OUTPUT_FIFOc_REG(c) \
+		(BLSP1_QUP_REG_BASE + 0x00000110 + 4 * (c))
+
+#define BLSP0_QUP_MX_INPUT_COUNT_REG	(BLSP0_QUP_REG_BASE + 0x00000200)
+#define BLSP1_QUP_MX_INPUT_COUNT_REG	(BLSP1_QUP_REG_BASE + 0x00000200)
+
+#define BLSP0_QUP_MX_OUTPUT_COUNT_REG	(BLSP0_QUP_REG_BASE + 0x00000100)
+#define BLSP1_QUP_MX_OUTPUT_COUNT_REG	(BLSP1_QUP_REG_BASE + 0x00000100)
+
+#define BLSP0_QUP_SW_RESET_REG		(BLSP0_QUP_REG_BASE + 0x0000000c)
+#define BLSP1_QUP_SW_RESET_REG		(BLSP1_QUP_REG_BASE + 0x0000000c)
 
-#define QUP5_BASE	((uint32_t)GSBI_QUP5_BASE)
-#define QUP6_BASE	((uint32_t)GSBI_QUP6_BASE)
-#define QUP7_BASE	((uint32_t)GSBI_QUP7_BASE)
-
-#define GSBI5_QUP5_REG_BASE		(QUP5_BASE + 0x00000000)
-#define GSBI6_QUP6_REG_BASE		(QUP6_BASE + 0x00000000)
-#define GSBI7_QUP7_REG_BASE		(QUP7_BASE + 0x00000000)
-
-#define GSBI5_REG_BASE			((uint32_t)(GSBI5_BASE + 0x00000000))
-#define GSBI6_REG_BASE			((uint32_t)(GSBI6_BASE + 0x00000000))
-#define GSBI7_REG_BASE			((uint32_t)(GSBI7_BASE + 0x00000000))
-
-#define BOOT_SPI_PORT5_BASE		QUP5_BASE
-#define BOOT_SPI_PORT6_BASE		QUP6_BASE
-#define BOOT_SPI_PORT7_BASE		QUP7_BASE
-
-#define GSBI5_SPI_CONFIG_REG		(GSBI5_QUP5_REG_BASE + 0x00000300)
-#define GSBI6_SPI_CONFIG_REG		(GSBI6_QUP6_REG_BASE + 0x00000300)
-#define GSBI7_SPI_CONFIG_REG		(GSBI7_QUP7_REG_BASE + 0x00000300)
-
-#define GSBI5_SPI_IO_CONTROL_REG	(GSBI5_QUP5_REG_BASE + 0x00000304)
-#define GSBI6_SPI_IO_CONTROL_REG	(GSBI6_QUP6_REG_BASE + 0x00000304)
-#define GSBI7_SPI_IO_CONTROL_REG	(GSBI7_QUP7_REG_BASE + 0x00000304)
-
-#define GSBI5_SPI_ERROR_FLAGS_REG	(GSBI5_QUP5_REG_BASE + 0x00000308)
-#define GSBI6_SPI_ERROR_FLAGS_REG	(GSBI6_QUP6_REG_BASE + 0x00000308)
-#define GSBI7_SPI_ERROR_FLAGS_REG	(GSBI7_QUP7_REG_BASE + 0x00000308)
-
-#define GSBI5_SPI_ERROR_FLAGS_EN_REG	(GSBI5_QUP5_REG_BASE + 0x0000030c)
-#define GSBI6_SPI_ERROR_FLAGS_EN_REG	(GSBI6_QUP6_REG_BASE + 0x0000030c)
-#define GSBI7_SPI_ERROR_FLAGS_EN_REG	(GSBI7_QUP7_REG_BASE + 0x0000030c)
-
-#define GSBI5_GSBI_CTRL_REG_REG		(GSBI5_REG_BASE + 0x00000000)
-#define GSBI6_GSBI_CTRL_REG_REG		(GSBI6_REG_BASE + 0x00000000)
-#define GSBI7_GSBI_CTRL_REG_REG		(GSBI7_REG_BASE + 0x00000000)
-
-#define GSBI5_QUP_CONFIG_REG		(GSBI5_QUP5_REG_BASE + 0x00000000)
-#define GSBI6_QUP_CONFIG_REG		(GSBI6_QUP6_REG_BASE + 0x00000000)
-#define GSBI7_QUP_CONFIG_REG		(GSBI7_QUP7_REG_BASE + 0x00000000)
-
-#define GSBI5_QUP_ERROR_FLAGS_REG	(GSBI5_QUP5_REG_BASE      + 0x0000001c)
-#define GSBI6_QUP_ERROR_FLAGS_REG	(GSBI6_QUP6_REG_BASE      + 0x0000001c)
-#define GSBI7_QUP_ERROR_FLAGS_REG	(GSBI7_QUP7_REG_BASE      + 0x0000001c)
-
-#define GSBI5_QUP_ERROR_FLAGS_EN_REG	(GSBI5_QUP5_REG_BASE + 0x00000020)
-#define GSBI6_QUP_ERROR_FLAGS_EN_REG	(GSBI6_QUP6_REG_BASE + 0x00000020)
-#define GSBI7_QUP_ERROR_FLAGS_EN_REG	(GSBI7_QUP7_REG_BASE + 0x00000020)
-
-#define GSBI5_QUP_OPERATIONAL_REG	(GSBI5_QUP5_REG_BASE + 0x00000018)
-#define GSBI6_QUP_OPERATIONAL_REG	(GSBI6_QUP6_REG_BASE + 0x00000018)
-#define GSBI7_QUP_OPERATIONAL_REG	(GSBI7_QUP7_REG_BASE + 0x00000018)
-
-#define GSBI5_QUP_IO_MODES_REG		(GSBI5_QUP5_REG_BASE + 0x00000008)
-#define GSBI6_QUP_IO_MODES_REG		(GSBI6_QUP6_REG_BASE + 0x00000008)
-#define GSBI7_QUP_IO_MODES_REG		(GSBI7_QUP7_REG_BASE + 0x00000008)
-
-#define GSBI5_QUP_STATE_REG		(GSBI5_QUP5_REG_BASE + 0x00000004)
-#define GSBI6_QUP_STATE_REG		(GSBI6_QUP6_REG_BASE + 0x00000004)
-#define GSBI7_QUP_STATE_REG		(GSBI7_QUP7_REG_BASE + 0x00000004)
-
-#define GSBI5_QUP_OUT_FIFO_WORD_CNT_REG	(GSBI5_QUP5_REG_BASE + 0x0000010c)
-#define GSBI6_QUP_OUT_FIFO_WORD_CNT_REG	(GSBI6_QUP6_REG_BASE + 0x0000010c)
-#define GSBI7_QUP_OUT_FIFO_WORD_CNT_REG	(GSBI7_QUP7_REG_BASE + 0x0000010c)
-
-#define GSBI5_QUP_IN_FIFO_WORD_CNT_REG	(GSBI5_QUP5_REG_BASE + 0x00000214)
-#define GSBI6_QUP_IN_FIFO_WORD_CNT_REG	(GSBI6_QUP6_REG_BASE + 0x00000214)
-#define GSBI7_QUP_IN_FIFO_WORD_CNT_REG	(GSBI7_QUP7_REG_BASE + 0x00000214)
-
-#define GSBI5_QUP_INPUT_FIFOc_REG(c) \
-		(GSBI5_QUP5_REG_BASE + 0x00000218 + 4 * (c))
-#define GSBI6_QUP_INPUT_FIFOc_REG(c) \
-		(GSBI6_QUP6_REG_BASE + 0x00000218 + 4 * (c))
-#define GSBI7_QUP_INPUT_FIFOc_REG(c) \
-		(GSBI7_QUP7_REG_BASE + 0x00000218 + 4 * (c))
-
-#define GSBI5_QUP_OUTPUT_FIFOc_REG(c) \
-		(GSBI5_QUP5_REG_BASE + 0x00000110 + 4 * (c))
-#define GSBI6_QUP_OUTPUT_FIFOc_REG(c) \
-		(GSBI6_QUP6_REG_BASE + 0x00000110 + 4 * (c))
-#define GSBI7_QUP_OUTPUT_FIFOc_REG(c) \
-		(GSBI7_QUP7_REG_BASE + 0x00000110 + 4 * (c))
-
-#define GSBI5_QUP_MX_INPUT_COUNT_REG	(GSBI5_QUP5_REG_BASE + 0x00000200)
-#define GSBI6_QUP_MX_INPUT_COUNT_REG	(GSBI6_QUP6_REG_BASE + 0x00000200)
-#define GSBI7_QUP_MX_INPUT_COUNT_REG	(GSBI7_QUP7_REG_BASE + 0x00000200)
-
-#define GSBI5_QUP_MX_OUTPUT_COUNT_REG	(GSBI5_QUP5_REG_BASE + 0x00000100)
-#define GSBI6_QUP_MX_OUTPUT_COUNT_REG	(GSBI6_QUP6_REG_BASE + 0x00000100)
-#define GSBI7_QUP_MX_OUTPUT_COUNT_REG	(GSBI7_QUP7_REG_BASE + 0x00000100)
-
-#define GSBI5_QUP_SW_RESET_REG		(GSBI5_QUP5_REG_BASE + 0x0000000c)
-#define GSBI6_QUP_SW_RESET_REG		(GSBI6_QUP6_REG_BASE + 0x0000000c)
-#define GSBI7_QUP_SW_RESET_REG		(GSBI7_QUP7_REG_BASE + 0x0000000c)
-
-#define CLK_CTL_REG_BASE		0x00900000
-#define GSBIn_RESET_REG(n) \
-		(CLK_CTL_REG_BASE      + 0x000029dc + 32 * ((n)-1))
-
-#define SFAB_AHB_S3_FCLK_CTL_REG \
-		(CLK_CTL_REG_BASE      + 0x0000216c)
-#define CFPB_CLK_NS_REG \
-		(CLK_CTL_REG_BASE      + 0x0000264c)
-#define SFAB_CFPB_S_HCLK_CTL_REG \
-		(CLK_CTL_REG_BASE      + 0x000026c0)
-#define CFPB_SPLITTER_HCLK_CTL_REG \
-		(CLK_CTL_REG_BASE      + 0x000026e0)
-#define CFPB0_HCLK_CTL_REG \
-		(CLK_CTL_REG_BASE      + 0x00002650)
-#define CFPB2_HCLK_CTL_REG \
-		(CLK_CTL_REG_BASE      + 0x00002658)
-#define GSBIn_HCLK_CTL_REG(n) \
-		(CLK_CTL_REG_BASE      + 0x000029c0 + 32 * ((n)-1))
-#define GSBIn_QUP_APPS_NS_REG(n) \
-	(CLK_CTL_REG_BASE      + 0x000029cc + 32 * ((n)-1))
-#define GSBIn_QUP_APPS_MD_REG(n) \
-		(CLK_CTL_REG_BASE      + 0x000029c8 + 32 * ((n)-1))
-#define CLK_HALT_CFPB_STATEB_REG \
-		(CLK_CTL_REG_BASE      + 0x00002fd0)
-
-#define GSBI5_HCLK				23
-#define GSBI6_HCLK				19
-#define GSBI7_HCLK				15
-#define GSBI5_QUP_APPS_CLK			20
-#define GSBI6_QUP_APPS_CLK			16
-#define GSBI7_QUP_APPS_CLK			12
-#define GSBI_CLK_BRANCH_ENA_MSK			(1 << 4)
-#define GSBI_CLK_BRANCH_ENA			(1 << 4)
-#define GSBI_CLK_BRANCH_DIS			(0 << 4)
-#define QUP_CLK_BRANCH_ENA_MSK			(1 << 9)
-#define QUP_CLK_BRANCH_ENA			(1 << 9)
-#define QUP_CLK_BRANCH_DIS			(0 << 9)
-#define CLK_ROOT_ENA_MSK			(1 << 11)
-#define CLK_ROOT_ENA				(1 << 11)
-#define CLK_ROOT_DIS				(0 << 11)
-
-#define QUP_STATE_VALID_BIT			2
-#define QUP_STATE_VALID				1
-#define QUP_STATE_MASK				0x3
 #define QUP_CONFIG_MINI_CORE_MSK		(0x0F << 8)
 #define QUP_CONFIG_MINI_CORE_SPI		(1 << 8)
-#define SPI_QUP_CONF_INPUT_MSK			(1 << 7)
-#define SPI_QUP_CONF_INPUT_ENA			(0 << 7)
-#define SPI_QUP_CONF_NO_INPUT			(1 << 7)
-#define SPI_QUP_CONF_OUTPUT_MSK			(1 << 6)
-#define SPI_QUP_CONF_OUTPUT_ENA			(0 << 6)
-#define SPI_QUP_CONF_NO_OUTPUT			(1 << 6)
-#define SPI_QUP_CONF_OUTPUT_ENA			(0 << 6)
-#define QUP_STATE_RESET_STATE			0x0
-#define QUP_STATE_RUN_STATE			0x1
-#define QUP_STATE_PAUSE_STATE			0x3
-#define SPI_BIT_WORD_MSK			0x1F
-#define SPI_8_BIT_WORD				0x07
-#define PROTOCOL_CODE_MSK			(0x07 << 4)
-#define PROTOCOL_CODE_SPI			(0x03 << 4)
-#define LOOP_BACK_MSK				(1 << 8)
-#define NO_LOOP_BACK				(0 << 8)
-#define SLAVE_OPERATION_MSK			(1 << 5)
-#define SLAVE_OPERATION				(0 << 5)
-#define CLK_ALWAYS_ON				(0 << 9)
-#define MX_CS_MODE				(0 << 8)
-#define NO_TRI_STATE				(1 << 0)
-#define OUTPUT_BIT_SHIFT_MSK			(1 << 16)
-#define OUTPUT_BIT_SHIFT_EN			(1 << 16)
-#define INPUT_BLOCK_MODE_MSK			(0x03 << 12)
-#define INPUT_BLOCK_MODE			(0x01 << 12)
-#define OUTPUT_BLOCK_MODE_MSK			(0x03 << 10)
-#define OUTPUT_BLOCK_MODE			(0x01 << 10)
-#define GSBI1_RESET				(1 << 0)
-#define GSBI1_RESET_MSK				0x1
-
-#define GSBI_M_VAL_SHFT				16
-#define GSBIn_M_VAL_MSK				(0xFF << GSBI_M_VAL_SHFT)
-#define GSBI_N_VAL_SHFT				16
-#define GSBIn_N_VAL_MSK				(0xFF << GSBI_N_VAL_SHFT)
-#define GSBI_D_VAL_SHFT				0
-#define GSBIn_D_VAL_MSK				(0xFF << GSBI_D_VAL_SHFT)
-#define MNCNTR_RST_MSK				(1 << 7)
-#define MNCNTR_RST_ENA				(1 << 7)
-#define MNCNTR_RST_DIS				(0 << 7)
-#define MNCNTR_MSK				(1 << 8)
-#define MNCNTR_EN				(1 << 8)
-#define MNCNTR_DIS				(0 << 8)
-#define MNCNTR_MODE_MSK				(0x3 << 5)
-#define MNCNTR_MODE_BYPASS			(0 << 5)
-#define MNCNTR_MODE_DUAL_EDGE			(0x2 << 5)
-#define GSBI_PRE_DIV_SEL_SHFT			3
-#define GSBIn_PRE_DIV_SEL_MSK			(0x3 << GSBI_PRE_DIV_SEL_SHFT)
-#define GSBIn_PLL_SRC_MSK			(0x03 << 0)
-#define GSBIn_PLL_SRC_PXO			(0 << 0)
-#define GSBIn_PLL_SRC_PLL8			(0x3 << 0)
-
-#define SPI_INPUT_FIRST_MODE			(1 << 9)
-#define SPI_IO_CONTROL_CLOCK_IDLE_HIGH		(1 << 10)
-#define QUP_DATA_AVAILABLE_FOR_READ		(1 << 5)
-#define QUP_OUTPUT_FIFO_NOT_EMPTY		(1 << 4)
-#define OUTPUT_SERVICE_FLAG			(1 << 8)
-#define INPUT_SERVICE_FLAG			(1 << 9)
-#define QUP_OUTPUT_FIFO_FULL			(1 << 6)
-#define QUP_INPUT_FIFO_NOT_EMPTY		(1 << 5)
+#define QUP_CONF_INPUT_MSK			(1 << 7)
+#define QUP_CONF_INPUT_ENA			(0 << 7)
+#define QUP_CONF_NO_INPUT			(1 << 7)
+#define QUP_CONF_OUTPUT_MSK			(1 << 6)
+#define QUP_CONF_OUTPUT_ENA			(0 << 6)
+#define QUP_CONF_NO_OUTPUT			(1 << 6)
+#define QUP_CONF_N_MASK				0x1F
+#define QUP_CONF_N_SPI_8_BIT_WORD		0x07
+
+#define SPI_CONFIG_INPUT_FIRST			(1 << 9)
+#define SPI_CONFIG_INPUT_FIRST_BACK		(0 << 9)
+#define SPI_CONFIG_LOOP_BACK_MSK		(1 << 8)
+#define SPI_CONFIG_NO_LOOP_BACK			(0 << 8)
+#define SPI_CONFIG_NO_SLAVE_OPER_MSK		(1 << 5)
+#define SPI_CONFIG_NO_SLAVE_OPER		(0 << 5)
+
+#define SPI_IO_CTRL_CLK_ALWAYS_ON		(0 << 9)
+#define SPI_IO_CTRL_MX_CS_MODE			(1 << 8)
+#define SPI_IO_CTRL_NO_TRI_STATE		(1 << 0)
+#define SPI_IO_CTRL_FORCE_CS_MSK		(1 << 11)
+#define SPI_IO_CTRL_FORCE_CS_EN			(1 << 11)
+#define SPI_IO_CTRL_FORCE_CS_DIS		(0 << 11)
+#define SPI_IO_CTRL_CLOCK_IDLE_HIGH		(1 << 10)
+
+#define QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK	(1 << 16)
+#define QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN	(1 << 16)
+#define QUP_IO_MODES_INPUT_MODE_MSK		(0x03 << 12)
+#define QUP_IO_MODES_INPUT_BLOCK_MODE		(0x01 << 12)
+#define QUP_IO_MODES_OUTPUT_MODE_MSK		(0x03 << 10)
+#define QUP_IO_MODES_OUTPUT_BLOCK_MODE		(0x01 << 10)
+
 #define SPI_INPUT_BLOCK_SIZE			4
 #define SPI_OUTPUT_BLOCK_SIZE			4
-#define GSBI5_SPI_CLK				21
-#define GSBI5_SPI_MISO				19
-#define GSBI5_SPI_MOSI				18
-#define GSBI5_SPI_CS_0				20
-#define GSBI5_SPI_CS_1				61
-#define GSBI5_SPI_CS_2				62
-#define GSBI5_SPI_CS_3				2
-#define GSBI6_SPI_CLK				30
-#define GSBI6_SPI_CS_0				29
-#define GSBI6_SPI_MISO				28
-#define GSBI6_SPI_MOSI				27
-#define GSBI7_SPI_CLK				9
-#define GSBI7_SPI_CS_0				8
-#define GSBI7_SPI_MISO				7
-#define GSBI7_SPI_MOSI				6
-
-#define MSM_GSBI_MAX_FREQ			51200000
-
-#define SPI_RESET_STATE				0
-#define SPI_RUN_STATE				1
-#define SPI_PAUSE_STATE				3
+
+#define MAX_COUNT_SIZE				0xffff
+
 #define SPI_CORE_RESET				0
 #define SPI_CORE_RUNNING			1
-#define GSBI_SPI_MODE_0				0
-#define GSBI_SPI_MODE_1				1
-#define GSBI_SPI_MODE_2				2
-#define GSBI_SPI_MODE_3				3
-#define GSBI5_SPI				0
-#define GSBI6_SPI				1
-#define GSBI7_SPI				2
-
-struct gsbi_spi {
-	unsigned int     spi_config;
-	unsigned int     io_control;
-	unsigned int     error_flags;
-	unsigned int     error_flags_en;
-	unsigned int     gsbi_ctrl;
-	unsigned int     qup_config;
-	unsigned int     qup_error_flags;
-	unsigned int     qup_error_flags_en;
-	unsigned int     qup_operational;
-	unsigned int     qup_io_modes;
-	unsigned int     qup_state;
-	unsigned int     qup_input_fifo;
-	unsigned int     qup_output_fifo;
-	unsigned int     qup_mx_input_count;
-	unsigned int     qup_mx_output_count;
-	unsigned int     qup_sw_reset;
-	unsigned int     qup_ns_reg;
-	unsigned int     qup_md_reg;
+#define SPI_MODE0				0
+#define SPI_MODE1				1
+#define SPI_MODE2				2
+#define SPI_MODE3				3
+#define BLSP0_SPI				0
+#define BLSP1_SPI				1
+
+struct blsp_spi {
+	void *spi_config;
+	void *io_control;
+	void *error_flags;
+	void *error_flags_en;
+	void *qup_config;
+	void *qup_error_flags;
+	void *qup_error_flags_en;
+	void *qup_operational;
+	void *qup_io_modes;
+	void *qup_state;
+	void *qup_input_fifo;
+	void *qup_output_fifo;
+	void *qup_mx_input_count;
+	void *qup_mx_output_count;
+	void *qup_sw_reset;
+	void *qup_ns_reg;
+	void *qup_md_reg;
+	void *qup_op_mask;
+	void *qup_deassert_wait;
 };
 
+
+#define SUCCESS		0
+
+#define DUMMY_DATA_VAL		0
+#define TIMEOUT_CNT		100
+
+#define ETIMEDOUT -10
+#define EINVAL -11
+#define EIO -12
+
+/* MX_INPUT_COUNT and MX_OUTPUT_COUNT are 16-bits. Zero has a special meaning
+ * (count function disabled) and does not hold significance in the count. */
+#define MAX_PACKET_COUNT	((64 * KiB) - 1)
+
+
 struct ipq_spi_slave {
 	struct spi_slave slave;
-	const struct gsbi_spi *regs;
+	const struct blsp_spi *regs;
 	unsigned int mode;
 	unsigned int initialized;
 	unsigned long freq;