soc/qualcomm/ipq40xx: Initial commit for IPQ40xx SoC support

Copy 'ipq806x' files as a template

BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Original-Commit-Id: dc6a5937953fe61cd4b5a99ca49f9371c4b712d4
Original-Change-Id: If171fcdd3b0561cb6b7dab5f8434de7ef711ea41
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/333178
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

squashed:

soc/qualcomm/ipq40xx: Update ipq806x/storm references

Since the files were taken from ipq806x/storm as
template. Update those references to reflect
ipq40xx/gale.

BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Original-Commit-Id: c6c76d184cc92c09e6826fbdc7d7fac59b2cb69b
Original-Change-Id: Ieae1bce25291243b4a6034d37a6949978f318997
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333293
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ie5794c48131ae562861074b406106734541880d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14644
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 173 insertions, 0 deletions

diff --git a/src/soc/qualcomm/ipq40xx/clock.c b/src/soc/qualcomm/ipq40xx/clock.c
new file mode 100644
index 0000000000..4d8d8e9adc
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/clock.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <delay.h>
+#include <soc/clock.h>
+#include <types.h>
+
+/**
+ * uart_pll_vote_clk_enable - enables PLL8
+ */
+void uart_pll_vote_clk_enable(unsigned int clk_dummy)
+{
+	setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8));
+
+	if (!clk_dummy)
+		while ((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0)
+			;
+}
+
+/**
+ * uart_set_rate_mnd - configures divider M and D values
+ *
+ * Sets the M, D parameters of the divider to generate the GSBI UART
+ * apps clock.
+ */
+static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m,
+		unsigned int n)
+{
+	/* Assert MND reset. */
+	setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
+	/* Program M and D values. */
+	write32(GSBIn_UART_APPS_MD_REG(gsbi_port), MD16(m, n));
+	/* Deassert MND reset. */
+	clrbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
+}
+
+/**
+ * uart_branch_clk_enable_reg - enables branch clock
+ *
+ * Enables branch clock for GSBI UART port.
+ */
+static void uart_branch_clk_enable_reg(unsigned int gsbi_port)
+{
+	setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9));
+}
+
+/**
+ * uart_local_clock_enable - configures N value and enables root clocks
+ *
+ * Sets the N parameter of the divider and enables root clock and
+ * branch clocks for GSBI UART port.
+ */
+static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n,
+					unsigned int m)
+{
+	unsigned int reg_val, uart_ns_val;
+	void *const reg = (void *)GSBIn_UART_APPS_NS_REG(gsbi_port);
+
+	/*
+	* Program the NS register, if applicable. NS registers are not
+	* set in the set_rate path because power can be saved by deferring
+	* the selection of a clocked source until the clock is enabled.
+	*/
+	reg_val = read32(reg); // REG(0x29D4+(0x20*((n)-1)))
+	reg_val &= ~(Uart_clk_ns_mask);
+	uart_ns_val =  NS(BIT_POS_31, BIT_POS_16, n, m, 5, 4, 3, 1, 2, 0, 3);
+	reg_val |= (uart_ns_val & Uart_clk_ns_mask);
+	write32(reg, reg_val);
+
+	/* enable MNCNTR_EN */
+	reg_val = read32(reg);
+	reg_val |= BIT(8);
+	write32(reg, reg_val);
+
+	/* set source to PLL8 running @384MHz */
+	reg_val = read32(reg);
+	reg_val |= 0x3;
+	write32(reg, reg_val);
+
+	/* Enable root. */
+	reg_val |= Uart_en_mask;
+	write32(reg, reg_val);
+	uart_branch_clk_enable_reg(gsbi_port);
+}
+
+/**
+ * uart_set_gsbi_clk - enables HCLK for UART GSBI port
+ */
+static void uart_set_gsbi_clk(unsigned int gsbi_port)
+{
+	setbits_le32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4));
+}
+
+/**
+ * uart_clock_config - configures UART clocks
+ *
+ * Configures GSBI UART dividers, enable root and branch clocks.
+ */
+void uart_clock_config(unsigned int gsbi_port, unsigned int m,
+		unsigned int n, unsigned int d, unsigned int clk_dummy)
+{
+	uart_set_rate_mnd(gsbi_port, m, d);
+	uart_pll_vote_clk_enable(clk_dummy);
+	uart_local_clock_enable(gsbi_port, n, m);
+	uart_set_gsbi_clk(gsbi_port);
+}
+
+/**
+ * nand_clock_config - configure NAND controller clocks
+ *
+ * Enable clocks to EBI2. Must be invoked before touching EBI2
+ * registers.
+ */
+void nand_clock_config(void)
+{
+	write32(EBI2_CLK_CTL_REG,
+		CLK_BRANCH_ENA(1) | ALWAYS_ON_CLK_BRANCH_ENA(1));
+
+	/* Wait for clock to stabilize. */
+	udelay(10);
+}
+
+/**
+ * usb_clock_config - configure USB controller clocks and reset the controller
+ */
+void usb_clock_config(void)
+{
+	/* Magic clock initialization numbers, nobody knows how they work... */
+	write32(USB30_MASTER_CLK_CTL_REG, 0x10);
+	write32(USB30_1_MASTER_CLK_CTL_REG, 0x10);
+	write32(USB30_MASTER_CLK_MD, 0x500DF);
+	write32(USB30_MASTER_CLK_NS, 0xE40942);
+	write32(USB30_MOC_UTMI_CLK_MD, 0x100D7);
+	write32(USB30_MOC_UTMI_CLK_NS, 0xD80942);
+	write32(USB30_MOC_UTMI_CLK_CTL, 0x10);
+	write32(USB30_1_MOC_UTMI_CLK_CTL, 0x10);
+
+	write32(USB30_RESET,
+		1 << 5 |		/* assert port2 HS PHY async reset */
+		1 << 4 |		/* assert master async reset */
+		1 << 3 |		/* assert sleep async reset */
+		1 << 2 |		/* assert MOC UTMI async reset */
+		1 << 1 |		/* assert power-on async reset */
+		1 << 0);		/* assert PHY async reset */
+	udelay(5);
+	write32(USB30_RESET, 0);	/* deassert all USB resets again */
+}