diff options
| author | Shelley Chen <shchen@google.com> | 2022-11-16 17:02:32 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-18 15:47:05 +0000 |
| commit | f6307ca9c210a2073ad59816b89ca37e06e3cf5a (patch) | |
| tree | 7d119c51377921693bfc58a501d1740f1df7511a /src/soc/qualcomm/common | |
| parent | b5af064f5493b6959d74dfbd948a4666d2a5cdc2 (diff) | |
soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs
On Herobrine, we will determine if we have an NVMe device based on SKU
id. Basically, if bit 0 is 2 (or Z), then we know that we have an
NVMe device and thus will need to go through PCIe initialization.
Otherwise, we know that we are booting an eMMC device.
BUG=b:254281839
BRANCH=None
TEST=build firmware image and boot and make sure we can boot up Tested
on villager, which does not have NVMe and made sure that it boots
still. Check cbmem dump to make sure that device configuration
entry is still low since it's not initializing PCIe devices:
40:device configuration 730,203 (1,295)
Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69690
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/common')
| -rw-r--r-- | src/soc/qualcomm/common/pcie_common.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c index 2f53e28028..940b206f1e 100644 --- a/src/soc/qualcomm/common/pcie_common.c +++ b/src/soc/qualcomm/common/pcie_common.c @@ -416,6 +416,9 @@ static enum cb_err qcom_dw_pcie_enable(struct qcom_pcie_cntlr_t *pcie) */ enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { + if (!mainboard_needs_pcie_init()) + return CB_ERR_NOT_IMPLEMENTED; + pcie_cntlr_cfg_t *pcierc = qcom_pcie_cfg.cntlr_cfg; pcie->ctrl_base = (uintptr_t)pcierc->dbi_base; return CB_SUCCESS; |