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authorJes Klinke <jbk@google.com>2022-02-22 16:00:09 -0800
committerJulius Werner <jwerner@chromium.org>2022-03-15 22:06:27 +0000
commit19baa9d51e4f1b36473dc750735eb6e5345bebda (patch)
tree60aada7f006fd73797b5c566d704e2b0ed5b728f /src/soc/qualcomm/common
parentca82e6161af7a453b512f35dd695a98084a1d7cf (diff)
i2c: Add configurable I2C transfer timeout
This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US, which controls how long to wait for an I2C devices to produce/accept all the data bytes in a single transfer. (The device can delay transfer by stretching the clock of the ack bit.) The default value of this new setting is 500ms. Existing code had timeouts anywhere from tens of milliseconds to a full second beween various drivers. Drivers can still have their own shorter timeouts for setup/communication with the I2C host controller (as opposed to transactions with I2C devices on the bus.) In general, the timeout is not meant to be reached except in situations where there is already serious problem with the boot, and serves to make sure that some useful diagnostic output is produced on the console. Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f Signed-off-by: Jes B. Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/common')
-rw-r--r--src/soc/qualcomm/common/include/soc/qup_se_handlers_common.h2
-rw-r--r--src/soc/qualcomm/common/qup_se_handler.c7
-rw-r--r--src/soc/qualcomm/common/qupv3_i2c.c4
-rw-r--r--src/soc/qualcomm/common/qupv3_spi.c4
4 files changed, 10 insertions, 7 deletions
diff --git a/src/soc/qualcomm/common/include/soc/qup_se_handlers_common.h b/src/soc/qualcomm/common/include/soc/qup_se_handlers_common.h
index bab7434f0d..a004c7944c 100644
--- a/src/soc/qualcomm/common/include/soc/qup_se_handlers_common.h
+++ b/src/soc/qualcomm/common/include/soc/qup_se_handlers_common.h
@@ -463,6 +463,6 @@ u32 qup_wait_for_s_irq(unsigned int bus);
void qup_m_cancel_and_abort(unsigned int bus);
void qup_s_cancel_and_abort(unsigned int bus);
int qup_handle_transfer(unsigned int bus, const void *dout, void *din,
- int size);
+ int size, struct stopwatch *timeout);
#endif /* __SOC_COMMON_QCOM_QUP_SE_H__ */
diff --git a/src/soc/qualcomm/common/qup_se_handler.c b/src/soc/qualcomm/common/qup_se_handler.c
index bb7be37cf0..7dd4f452af 100644
--- a/src/soc/qualcomm/common/qup_se_handler.c
+++ b/src/soc/qualcomm/common/qup_se_handler.c
@@ -149,15 +149,14 @@ void qup_s_cancel_and_abort(unsigned int bus)
}
}
-int qup_handle_transfer(unsigned int bus, const void *dout, void *din, int size)
+int qup_handle_transfer(unsigned int bus, const void *dout, void *din, int size,
+ struct stopwatch *timeout)
{
unsigned int m_irq;
- struct stopwatch sw;
unsigned int rx_rem_bytes = din ? size : 0;
unsigned int tx_rem_bytes = dout ? size : 0;
struct qup_regs *regs = qup[bus].regs;
- stopwatch_init_msecs_expire(&sw, 1000);
do {
m_irq = qup_wait_for_m_irq(bus);
if ((m_irq & M_RX_FIFO_WATERMARK_EN) ||
@@ -172,7 +171,7 @@ int qup_handle_transfer(unsigned int bus, const void *dout, void *din, int size)
break;
}
write32(&regs->geni_m_irq_clear, m_irq);
- } while (!stopwatch_expired(&sw));
+ } while (!stopwatch_expired(timeout));
if (!(m_irq & M_CMD_DONE_EN) || tx_rem_bytes || rx_rem_bytes) {
printk(BIOS_INFO, "%s:Error: Transfer failed\n", __func__);
diff --git a/src/soc/qualcomm/common/qupv3_i2c.c b/src/soc/qualcomm/common/qupv3_i2c.c
index 606b3bf935..8f0880e35d 100644
--- a/src/soc/qualcomm/common/qupv3_i2c.c
+++ b/src/soc/qualcomm/common/qupv3_i2c.c
@@ -117,6 +117,7 @@ static int i2c_do_xfer(unsigned int bus, struct i2c_msg segment,
unsigned int master_cmd_reg_val = (cmd << M_OPCODE_SHFT);
struct qup_regs *regs = qup[bus].regs;
void *dout = NULL, *din = NULL;
+ struct stopwatch timeout;
if (!(segment.flags & I2C_M_RD)) {
write32(&regs->i2c_tx_trans_len, segment.len);
@@ -130,7 +131,8 @@ static int i2c_do_xfer(unsigned int bus, struct i2c_msg segment,
master_cmd_reg_val |= (prams & M_PARAMS_MSK);
write32(&regs->geni_m_cmd0, master_cmd_reg_val);
- return qup_handle_transfer(bus, dout, din, segment.len);
+ stopwatch_init_usecs_expire(&timeout, CONFIG_I2C_TRANSFER_TIMEOUT_US);
+ return qup_handle_transfer(bus, dout, din, segment.len, &timeout);
}
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
diff --git a/src/soc/qualcomm/common/qupv3_spi.c b/src/soc/qualcomm/common/qupv3_spi.c
index c69ecf9eaa..1bb5c75e5e 100644
--- a/src/soc/qualcomm/common/qupv3_spi.c
+++ b/src/soc/qualcomm/common/qupv3_spi.c
@@ -83,6 +83,7 @@ int qup_spi_xfer(const struct spi_slave *slave, const void *dout,
int size;
unsigned int se_bus = slave->bus;
struct qup_regs *regs = qup[se_bus].regs;
+ struct stopwatch timeout;
if ((bytes_in == 0) && (bytes_out == 0))
return 0;
@@ -114,7 +115,8 @@ int qup_spi_xfer(const struct spi_slave *slave, const void *dout,
qup_setup_m_cmd(se_bus, m_cmd, m_param);
- if (qup_handle_transfer(se_bus, dout, din, size))
+ stopwatch_init_msecs_expire(&timeout, 1000);
+ if (qup_handle_transfer(se_bus, dout, din, size, &timeout))
return -1;
qup_spi_xfer(slave, dout + size, MAX((int)bytes_out - size, 0),