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authorArthur Heymans <arthur@aheymans.xyz>2022-11-03 10:56:45 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-11-04 19:17:49 +0000
commit8c740b08a373163cda73973b63ae70685458d56b (patch)
tree34827e1dbedf6100d4c949d6eef998eaf6424f2a /src/soc/qualcomm/common
parent9948c521a63148e49d850d2ac760f245007908a3 (diff)
lib/coreboot_table: Rename lb_fill_pcie
By convention 'fill_lb_xxx' is used. Change-Id: I046016b3898308bb56b4ad6a5834ab942fdd50f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69183 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/common')
-rw-r--r--src/soc/qualcomm/common/pcie_common.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c
index e27b0fcbfb..2f53e28028 100644
--- a/src/soc/qualcomm/common/pcie_common.c
+++ b/src/soc/qualcomm/common/pcie_common.c
@@ -414,7 +414,7 @@ static enum cb_err qcom_dw_pcie_enable(struct qcom_pcie_cntlr_t *pcie)
* Fill coreboot table with PCIe info.
* It allows exporting this info to payloads.
*/
-enum cb_err lb_fill_pcie(struct lb_pcie *pcie)
+enum cb_err fill_lb_pcie(struct lb_pcie *pcie)
{
pcie_cntlr_cfg_t *pcierc = qcom_pcie_cfg.cntlr_cfg;
pcie->ctrl_base = (uintptr_t)pcierc->dbi_base;