soc/qualcomm/common/usb: Add support for common USB driver

Add common USB driver for qualcomm soc sc7180 and sc7280.

This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy.

BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7180 and
sc7280 development board

Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: I1013ded22855286220cfa747cb25418070fe85a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

4 files changed, 204 insertions, 0 deletions

diff --git a/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h b/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h
new file mode 100644
index 0000000000..fc1721afa9
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <console/console.h>
+
+/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */
+#define USB3_PCS_PHYSTATUS		BIT(6)
+
+struct qmp_phy_init_tbl {
+	u32 *address;
+	u32 val;
+};
+
+struct ss_usb_phy_reg {
+	/* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */
+	const struct qmp_phy_init_tbl *serdes_tbl;
+	int serdes_tbl_num;
+
+	const struct qmp_phy_init_tbl *tx_tbl;
+	int tx_tbl_num;
+
+	const struct qmp_phy_init_tbl *rx_tbl;
+	int rx_tbl_num;
+
+	const struct qmp_phy_init_tbl *pcs_tbl;
+	int pcs_tbl_num;
+
+	struct usb3_phy_pcs_reg_layout *qmp_pcs_reg;
+};
+
+void ss_qmp_phy_init(void);
diff --git a/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h b/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h
new file mode 100644
index 0000000000..dd4a736bd0
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <console/console.h>
+
+#define PORT_TUNE1_MASK				0xf0
+
+/* QUSB2PHY_PWR_CTRL1 register related bits */
+#define POWER_DOWN				BIT(0)
+
+/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */
+#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS		0x4
+
+/* STAT5 register bits */
+#define VSTATUS_PLL_LOCK_STATUS_MASK		BIT(0)
+
+/* QUSB PHY register values */
+#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO	0x03
+#define QUSB2PHY_PLL_CLOCK_INVERTERS		0x7c
+#define QUSB2PHY_PLL_CMODE			0x80
+#define QUSB2PHY_PLL_LOCK_DELAY			0x0a
+#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO		0x19
+#define QUSB2PHY_PLL_BIAS_CONTROL_1		0x40
+#define QUSB2PHY_PLL_BIAS_CONTROL_2		0x22
+#define QUSB2PHY_PWR_CTRL2			0x21
+#define QUSB2PHY_IMP_CTRL1			0x08
+#define QUSB2PHY_IMP_CTRL2			0x58
+#define QUSB2PHY_PORT_TUNE1			0xc5
+#define QUSB2PHY_PORT_TUNE2			0x29
+#define QUSB2PHY_PORT_TUNE3			0xca
+#define QUSB2PHY_PORT_TUNE4			0x04
+#define QUSB2PHY_PORT_TUNE5			0x03
+#define QUSB2PHY_CHG_CTRL2			0x30
+
+
+#define QFPROM_BASE			0x00780000
+#define QUSB_PRIM_PHY_BASE		0x088e3000
+#define QUSB_PRIM_PHY_DIG_BASE		0x088e3200
+
+#define HS_USB_PRIM_PHY_BASE  QUSB_PRIM_PHY_BASE
+
+struct usb_board_data {
+	/* Register values going to override from the boardfile */
+	u32 pll_bias_control_2;
+	u32 imp_ctrl1;
+	u32 port_tune1;
+};
+
+struct usb_qusb_phy_dig {
+	u8 rsvd1[16];
+	u32 pwr_ctrl1;
+	u32 pwr_ctrl2;
+	u8 rsvd2[8];
+	u32 imp_ctrl1;
+	u32 imp_ctrl2;
+	u8 rsvd3[20];
+	u32 chg_ctrl2;
+	u32 tune1;
+	u32 tune2;
+	u32 tune3;
+	u32 tune4;
+	u32 tune5;
+	u8 rsvd4[44];
+	u32 debug_ctrl2;
+	u8 rsvd5[28];
+	u32 debug_stat5;
+};
+check_member(usb_qusb_phy_dig, tune5, 0x50);
+check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80);
+check_member(usb_qusb_phy_dig, debug_stat5, 0xA0);
+
+struct usb_qusb_phy_pll {
+	u8 rsvd0[4];
+	u32 analog_controls_two;
+	u8 rsvd1[36];
+	u32 cmode;
+	u8 rsvd2[132];
+	u32 dig_tim;
+	u8 rsvd3[204];
+	u32 lock_delay;
+	u8 rsvd4[4];
+	u32 clock_inverters;
+	u8 rsvd5[4];
+	u32 bias_ctrl_1;
+	u32 bias_ctrl_2;
+};
+check_member(usb_qusb_phy_pll, cmode, 0x2C);
+check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198);
+check_member(usb_qusb_phy_pll, dig_tim, 0xB4);
+
+struct hs_usb_phy_reg {
+	struct usb_qusb_phy_pll *phy_pll;
+	struct usb_qusb_phy_dig *phy_dig;
+	struct usb_board_data *board_data;
+	u32 efuse_offset;
+};
diff --git a/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h b/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h
new file mode 100644
index 0000000000..de0b385c0b
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <console/console.h>
+
+struct usb_board_data {
+	/*Register values going to override from the boardfile*/
+	u8 parameter_override_x0;
+	u8 parameter_override_x1;
+	u8 parameter_override_x2;
+	u8 parameter_override_x3;
+};
+
+struct hs_usb_phy_reg {
+	u8 rsvd1[60];
+	u32 utmi_ctrl0;
+	u32 utmi_ctrl1;
+	u8 rsvd2[12];
+	u32 utmi_ctrl5;
+	u32 hs_phy_ctrl_common0;
+	u32 hs_phy_ctrl_common1;
+	u32 hs_phy_ctrl_common2;
+	u32 hs_phy_ctrl1;
+	u32 hs_phy_ctrl2;
+	u8 rsvd3[4];
+	u32 hs_phy_override_x0;
+	u32 hs_phy_override_x1;
+	u32 hs_phy_override_x2;
+	u32 hs_phy_override_x3;
+	u8 rsvd4[24];
+	u32 cfg0;
+	u8 rsvd5[8];
+	u32 refclk_ctrl;
+};
+check_member(hs_usb_phy_reg, utmi_ctrl0, 0x03c);
+check_member(hs_usb_phy_reg, utmi_ctrl1, 0x040);
+check_member(hs_usb_phy_reg, utmi_ctrl5, 0x050);
+check_member(hs_usb_phy_reg, hs_phy_ctrl2, 0x064);
+check_member(hs_usb_phy_reg, hs_phy_override_x0, 0x06c);
+check_member(hs_usb_phy_reg, hs_phy_override_x3, 0x078);
+check_member(hs_usb_phy_reg, cfg0, 0x094);
+check_member(hs_usb_phy_reg, refclk_ctrl, 0x0a0);
diff --git a/src/soc/qualcomm/common/include/soc/usb/usb_common.h b/src/soc/qualcomm/common/include/soc/usb/usb_common.h
new file mode 100644
index 0000000000..662d4889a6
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/usb/usb_common.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "qmp_usb_phy.h"
+
+/* QSCRATCH_GENERAL_CFG register bit offset */
+#define PIPE_UTMI_CLK_SEL			BIT(0)
+#define PIPE3_PHYSTATUS_SW			BIT(3)
+#define PIPE_UTMI_CLK_DIS			BIT(8)
+
+/* Global USB3 Control  Registers */
+#define DWC3_GUSB3PIPECTL_DELAYP1TRANS		BIT(18)
+#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX		BIT(27)
+#define DWC3_GCTL_PRTCAPDIR(n)			((n) << 12)
+#define DWC3_GCTL_PRTCAP_OTG			3
+#define DWC3_GCTL_PRTCAP_HOST			1
+
+/* Global USB2 PHY Configuration Register */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM(n)		((n) << 10)
+#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK	DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
+#define DWC3_GUSB2PHYCFG_PHYIF(n)		((n) << 3)
+#define DWC3_GUSB2PHYCFG_PHYIF_MASK		DWC3_GUSB2PHYCFG_PHYIF(1)
+#define USBTRDTIM_UTMI_8_BIT			9
+#define UTMI_PHYIF_8_BIT			0
+
+#define DWC3_GCTL_SCALEDOWN(n)			((n) << 4)
+#define DWC3_GCTL_SCALEDOWN_MASK		DWC3_GCTL_SCALEDOWN(3)
+#define DWC3_GCTL_DISSCRAMBLE			(1 << 3)
+#define DWC3_GCTL_U2EXIT_LFPS			(1 << 2)
+#define DWC3_GCTL_DSBLCLKGTNG			(1 << 0)
+
+void hs_usb_phy_init(void  *board_data);
+void setup_usb_host0(void  *board_data);
+
+/* Call reset_ before setup_ */
+void reset_usb0(void);