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authorJonathan Zhang <jonzhang@fb.com>2020-05-12 15:58:45 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-06-25 11:53:34 +0000
commited624c71582ff420362b95c8da52c303b446428d (patch)
tree6092dcd623bab708bb730ce8a470ffe0d67b90d5 /src/soc/nvidia
parenteba0433b1707904507bd62cf547450d9e2fd203e (diff)
soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBs
Support display of CPX-SP specific HOBs (when CONFIG_DISPLAY_HOBS is selected, and UPD parameters (when CONFIG_DISPLAY_UPD_DATA is selected). Such display is used for FSP debugging purpose. It adds small amount of boot time. Some UPD display log excerpts: UPD values for SiliconInit: 0x04: BifurcationPcie0 0x03: BifurcationPcie1 Some HOB display log excerpts: === FSP HOBs === 0x758df000: hob_list_ptr 0x758df000, 0x00000038 bytes: HOB_TYPE_HANDOFF 0x758df038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41348 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/nvidia')
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