arm(64): Replace write32() and friends with writel()

This patch is a raw application of the following spatch to the
directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>,
src/soc/<arm(64)-soc> and src/drivers/gic:

@@
expression A, V;
@@
- write32(V, A)
+ writel(V, A)
@@
expression A, V;
@@
- write16(V, A)
+ writew(V, A)
@@
expression A, V;
@@
- write8(V, A)
+ writeb(V, A)

This replaces all uses of write{32,16,8}() with write{l,w,b}()
which is currently equivalent and much more common. This is a
preparatory step that will allow us to easier flip them all at once to
the new write32(a,v) model.

BRANCH=none
BUG=chromium:451388
TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky.

Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24
Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254862
Reviewed-on: http://review.coreboot.org/9834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

25 files changed, 244 insertions, 338 deletions

diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c
index 3fc0ef7de1..292d21d02f 100644
--- a/src/soc/nvidia/tegra/apbmisc.c
+++ b/src/soc/nvidia/tegra/apbmisc.c
@@ -26,12 +26,12 @@ static struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE;
 
 void enable_jtag(void)
 {
-	write32(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl);
+	writel(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl);
 }
 
 void clamp_tristate_inputs(void)
 {
-	write32(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global);
+	writel(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global);
 }
 
 void tegra_revision_info(struct tegra_revision *id)
diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c
index 009334f74c..8179580add 100644
--- a/src/soc/nvidia/tegra/gpio.c
+++ b/src/soc/nvidia/tegra/gpio.c
@@ -67,8 +67,8 @@ static void gpio_write_port(int index, size_t offset, u32 mask, u32 value)
 	u32 new_reg = (reg & ~mask) | (value & mask);
 
 	if (new_reg != reg) {
-		write32(new_reg, (u8 *)&gpio_banks[bank] + offset +
-			port * sizeof(u32));
+		writel(new_reg,
+		       (u8 *)&gpio_banks[bank] + offset + port * sizeof(u32));
 	}
 }
 
diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c
index 6f9142ca6d..b9a5f42a37 100644
--- a/src/soc/nvidia/tegra/i2c.c
+++ b/src/soc/nvidia/tegra/i2c.c
@@ -40,9 +40,9 @@ static void do_bus_clear(int bus)
 	// 4. Set TERMINATE condition (1 = IMMEDIATE)
 	bc = read32(&regs->bus_clear_config);
 	bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE;
-	write32(bc, &regs->bus_clear_config);
+	writel(bc, &regs->bus_clear_config);
 	// 4.1 Set MSTR_CONFIG_LOAD and wait for clear
-	write32(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load);
+	writel(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load);
 	for (i = 0; i < timeout_ms * 10 && (read32(&regs->config_load) &
 			I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE); i++) {
 		printk(BIOS_DEBUG, "%s: wait for MSTR_CONFIG_LOAD to clear\n",
@@ -50,7 +50,7 @@ static void do_bus_clear(int bus)
 		udelay(100);
 	}
 	// 5. Set ENABLE to start the bus clear op
-	write32(bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE, &regs->bus_clear_config);
+	writel(bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE, &regs->bus_clear_config);
 	for (i = 0; i < timeout_ms * 10 && (read32(&regs->bus_clear_config) &
 			I2C_BUS_CLEAR_CONFIG_BC_ENABLE); i++) {
 		printk(BIOS_DEBUG, "%s: wait for bus clear completion\n",
@@ -74,7 +74,7 @@ static int tegra_i2c_send_recv(int bus, int read,
 		rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT;
 
 		while (header_words && tx_empty) {
-			write32(*headers++, &regs->tx_packet_fifo);
+			writel(*headers++, &regs->tx_packet_fifo);
 			header_words--;
 			tx_empty--;
 		}
@@ -96,7 +96,7 @@ static int tegra_i2c_send_recv(int bus, int read,
 					int todo = MIN(data_len, sizeof(word));
 
 					memcpy(&word, data, todo);
-					write32(word, &regs->tx_packet_fifo);
+					writel(word, &regs->tx_packet_fifo);
 					data_len -= todo;
 					data += sizeof(word);
 					tx_empty--;
@@ -208,5 +208,5 @@ void i2c_init(unsigned bus)
 {
 	struct tegra_i2c_regs * const regs = tegra_i2c_info[bus].base;
 
-	write32(I2C_CNFG_PACKET_MODE_EN, &regs->cnfg);
+	writel(I2C_CNFG_PACKET_MODE_EN, &regs->cnfg);
 }
diff --git a/src/soc/nvidia/tegra/pingroup.c b/src/soc/nvidia/tegra/pingroup.c
index 858cb44e34..c856c173ac 100644
--- a/src/soc/nvidia/tegra/pingroup.c
+++ b/src/soc/nvidia/tegra/pingroup.c
@@ -26,7 +26,7 @@ static uint32_t *pingroup_regs = (void *)TEGRA_APB_PINGROUP_BASE;
 
 void pingroup_set_config(int group_index, uint32_t config)
 {
-	write32(config, &pingroup_regs[group_index]);
+	writel(config, &pingroup_regs[group_index]);
 }
 
 uint32_t pingroup_get_config(int group_index)
diff --git a/src/soc/nvidia/tegra/pinmux.c b/src/soc/nvidia/tegra/pinmux.c
index 6e4b3ff195..a88a063cac 100644
--- a/src/soc/nvidia/tegra/pinmux.c
+++ b/src/soc/nvidia/tegra/pinmux.c
@@ -26,7 +26,7 @@ static uint32_t *pinmux_regs = (void *)TEGRA_APB_PINMUX_BASE;
 
 void pinmux_set_config(int pin_index, uint32_t config)
 {
-	write32(config, &pinmux_regs[pin_index]);
+	writel(config, &pinmux_regs[pin_index]);
 }
 
 uint32_t pinmux_get_config(int pin_index)
diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c
index 3268ee1a74..c666c40f3b 100644
--- a/src/soc/nvidia/tegra/usb.c
+++ b/src/soc/nvidia/tegra/usb.c
@@ -126,7 +126,7 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t
 {
 	int timeout = 1000;
 
-	write32(1 << 1, &usb->ehci_usbcmd);	/* Host Controller Reset */
+	writel(1 << 1, &usb->ehci_usbcmd);	/* Host Controller Reset */
 	/* TODO: Resets are long, find way to parallelize... or just use XHCI */
 	while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1))
 		/* wait for HC to reset */;
@@ -137,11 +137,11 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t
 	}
 
 	/* Controller mode: HOST */
-	write32(3 << 0, &usb->usb_mode);
+	writel(3 << 0, &usb->usb_mode);
 	/* Parallel transceiver selct */
-	write32(type << 29, &usb->lpm_ctrl);
+	writel(type << 29, &usb->lpm_ctrl);
 	/* Tx FIFO Burst thresh */
-	write32(0x10 << 16, &usb->tx_fill_tuning);
+	writel(0x10 << 16, &usb->tx_fill_tuning);
 }
 
 /* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */
@@ -157,61 +157,27 @@ void usb_setup_utmip(void *usb_base)
 	udelay(1);
 
 	/* Take stuff out of pwrdn and add some magic numbers from U-Boot */
-	write32(0x8 << 25 |		/* HS slew rate [10:4] */
-		0x3 << 22 |		/* HS driver output 'SETUP' [6:4] */
-		0 << 21 |		/* LS bias selection */
-		0 << 18 |		/* PDZI pwrdn */
-		0 << 16 |		/* PD2 pwrdn */
-		0 << 14 |		/* PD pwrdn */
-		1 << 13 |		/* (rst) HS receiver terminations */
-		0x1 << 10 |		/* (rst) LS falling slew rate */
-		0x1 << 8 |		/* (rst) LS rising slew rate */
-		0x4 << 0 |		/* HS driver output 'SETUP' [3:0] */
-		0, &usb->utmip.xcvr0);
-	write32(0x7 << 18 |		/* Termination range adjustment */
-		0 << 4 |		/* PDDR pwrdn */
-		0 << 2 |		/* PDCHRP pwrdn */
-		0 << 0 |		/* PDDISC pwrdn */
-		0, &usb->utmip.xcvr1);
-	write32(1 << 19 |		/* FS send initial J before sync(?) */
-		1 << 16 |		/* (rst) Allow stuff error on SoP */
-		1 << 9 |		/* (rst) Check disc only on EoP */
-		0, &usb->utmip.tx);
-	write32(0x2 << 30 |		/* (rst) Keep pattern on active */
-		1 << 28 |		/* (rst) Realign inertia on pkt */
-		0x1 << 24 |		/* (rst) edges-1 to move sampling */
-		0x3 << 21 |		/* (rst) squelch delay on EoP */
-		0x11 << 15 |		/* cycles until IDLE */
-		0x10 << 10 |		/* elastic input depth */
-		0, &usb->utmip.hsrx0);
+	writel(0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0,
+	       &usb->utmip.xcvr0);
+	writel(0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0, &usb->utmip.xcvr1);
+	writel(1 << 19 | 1 << 16 | 1 << 9 | 0, &usb->utmip.tx);
+	writel(0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0,
+	       &usb->utmip.hsrx0);
 
 	/* U-Boot claims the USBD values for these are used across all UTMI+
 	 * PHYs. That sounds so horribly wrong that I'm not going to implement
 	 * it, but keep it in mind if we're ever not using the USBD port. */
-	write32(0x1 << 24 |		/* HS disconnect detect level [2] */
-		1 << 23 |		/* (rst) IDPD value */
-		1 << 22 |		/* (rst) IDPD select */
-		1 << 11 |		/* (rst) OTG pwrdn */
-		0 << 10 |		/* bias pwrdn */
-		0x1 << 2 |		/* HS disconnect detect level [1:0] */
-		0x2 << 0 |		/* HS squelch detect level */
-		0, &usb->utmip.bias0);
-
-	write32(khz / 2200 << 3 |	/* bias pwrdn cycles (20us?) */
-		1 << 2 |		/* (rst) VBUS wakeup pwrdn */
-		0 << 0 |		/* PDTRK pwrdn */
-		0, &usb->utmip.bias1);
-
-	write32(0xffff << 16 |		/* (rst) */
-		25 * khz / 10 << 0 |	/* TODO: what's this, really? */
-		0, &usb->utmip.debounce);
+	writel(0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0,
+	       &usb->utmip.bias0);
+
+	writel(khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0, &usb->utmip.bias1);
+
+	writel(0xffff << 16 | 25 * khz / 10 << 0 | 0, &usb->utmip.debounce);
 
 	udelay(1);
 	setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */
 
-	write32(1 << 12 |		/* UTMI+ enable */
-		0 << 11 |		/* UTMI+ reset */
-		0, &usb->suspend_ctrl);
+	writel(1 << 12 | 0 << 11 | 0, &usb->suspend_ctrl);
 
 	usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
 	printk(BIOS_DEBUG, "USB controller @ %p set up with UTMI+ PHY\n",usb_base);
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index 225a764431..dc1d1dbe8a 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -186,11 +186,11 @@ void clock_init_arm_generic_timer(void)
 	set_cntfrq(freq);
 
 	// Record the system timer frequency.
-	write32(freq, &sysctr->cntfid0);
+	writel(freq, &sysctr->cntfid0);
 	// Enable the system counter.
 	uint32_t cntcr = read32(&sysctr->cntcr);
 	cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG;
-	write32(cntcr, &sysctr->cntcr);
+	writel(cntcr, &sysctr->cntcr);
 }
 
 #define SOR0_CLK_SEL0			(1 << 14)
@@ -243,25 +243,14 @@ static void init_utmip_pll(void)
 	clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
 	udelay(1);
 
-	write32(80 << 16 |			/* (rst) phy_divn */
-		1 << 8 |			/* (rst) phy_divm */
-		0, &clk_rst->utmip_pll_cfg0);	/* 960MHz * 1 / 80 == 12 MHz */
+	writel(80 << 16 | 1 << 8 | 0, &clk_rst->utmip_pll_cfg0);	/* 960MHz * 1 / 80 == 12 MHz */
 
-	write32(CEIL_DIV(khz, 8000) << 27 |	/* pllu_enbl_cnt / 8 (1us) */
-		0 << 16 |			/* PLLU pwrdn */
-		0 << 14 |			/* pll_enable pwrdn */
-		0 << 12 |			/* pll_active pwrdn */
-		CEIL_DIV(khz, 102) << 0 |	/* phy_stbl_cnt / 256 (2.5ms) */
-		0, &clk_rst->utmip_pll_cfg1);
+	writel(CEIL_DIV(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | CEIL_DIV(khz, 102) << 0 | 0,
+	       &clk_rst->utmip_pll_cfg1);
 
 	/* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */
-	write32(0 << 24 |			/* SAMP_D/XDEV pwrdn */
-		CEIL_DIV(khz, 3200) << 18 |	/* phy_actv_cnt / 16 (5us) */
-		CEIL_DIV(khz, 256) << 6 |	/* pllu_stbl_cnt / 256 (1ms) */
-		0 << 4 |			/* SAMP_C/USB3 pwrdn */
-		0 << 2 |			/* SAMP_B/XHOST pwrdn */
-		0 << 0 |			/* SAMP_A/USBD pwrdn */
-		0, &clk_rst->utmip_pll_cfg2);
+	writel(0 << 24 | CEIL_DIV(khz, 3200) << 18 | CEIL_DIV(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0,
+	       &clk_rst->utmip_pll_cfg2);
 
 	setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
 }
@@ -398,8 +387,8 @@ clock_display(u32 frequency)
  * been determined through trial and error (must lead to div 13 at 24MHz). */
 void clock_early_uart(void)
 {
-	write32(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE |
-		CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), &clk_rst->clk_src_uarta);
+	writel(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900),
+	       &clk_rst->clk_src_uarta);
 	setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA);
 	udelay(2);
 	clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA);
@@ -486,28 +475,24 @@ void clock_cpu0_config(void *entry)
 {
 	void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100;
 
-	write32((uintptr_t)_estack, &maincpu_stack_pointer);
-	write32((uintptr_t)entry, &maincpu_entry_point);
-	write32((uintptr_t)&maincpu_setup, evp_cpu_reset);
+	writel((uintptr_t)_estack, &maincpu_stack_pointer);
+	writel((uintptr_t)entry, &maincpu_entry_point);
+	writel((uintptr_t)&maincpu_setup, evp_cpu_reset);
 
 	/* Set active CPU cluster to G */
 	clrbits_le32(&flow->cluster_control, 1);
 
 	// Set up cclk_brst and divider.
-	write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) |
-		(CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) |
-		(CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) |
-		(CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) |
-		(CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28),
-		&clk_rst->cclk_brst_pol);
-	write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB,
-		&clk_rst->super_cclk_div);
+	writel((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28),
+	       &clk_rst->cclk_brst_pol);
+	writel(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB,
+	       &clk_rst->super_cclk_div);
 
 	// Enable the clocks for CPUs 0-3.
 	uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr);
 	cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP |
 			 CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP;
-	write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr);
+	writel(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr);
 
 	// Enable other CPU related clocks.
 	setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU);
@@ -518,36 +503,23 @@ void clock_cpu0_config(void *entry)
 void clock_cpu0_remove_reset(void)
 {
 	// Disable the reset on the non-CPU parts of the fast cluster.
-	write32(CRC_RST_CPUG_CLR_NONCPU,
-		&clk_rst->rst_cpug_cmplx_clr);
+	writel(CRC_RST_CPUG_CLR_NONCPU, &clk_rst->rst_cpug_cmplx_clr);
 	// Disable the various resets on the CPUs.
-	write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 |
-		CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 |
-		CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 |
-		CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 |
-		CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 |
-		CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 |
-		CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 |
-		CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 |
-		CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
-		&clk_rst->rst_cpug_cmplx_clr);
+	writel(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
+	       &clk_rst->rst_cpug_cmplx_clr);
 
 	// Disable the reset on the non-CPU parts of the slow cluster.
-	write32(CRC_RST_CPULP_CLR_NONCPU,
-		&clk_rst->rst_cpulp_cmplx_clr);
+	writel(CRC_RST_CPULP_CLR_NONCPU, &clk_rst->rst_cpulp_cmplx_clr);
 	// Disable the various resets on the LP CPU.
-	write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 |
-		CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 |
-		CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG,
-		&clk_rst->rst_cpulp_cmplx_clr);
+	writel(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG,
+	       &clk_rst->rst_cpulp_cmplx_clr);
 }
 
 void clock_halt_avp(void)
 {
 	for (;;) {
-		write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ |
-			FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
-			&flow->halt_cop_events);
+		writel(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
+		       &flow->halt_cop_events);
 	}
 }
 
@@ -564,15 +536,12 @@ void clock_init(void)
 
 	/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
 	 * features section in the TRM). */
-	write32(TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT |
-		TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT,
-		&clk_rst->clk_sys_rate);
-	write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) <<
-		PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN |
-		PLL_OUT_RSTN, &clk_rst->pllc_out);
-	write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT |
-		SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
-		&clk_rst->sclk_brst_pol);		/* sclk = 300 MHz */
+	writel(TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT | TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT,
+	       &clk_rst->clk_sys_rate);
+	writel(CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN,
+	       &clk_rst->pllc_out);
+	writel(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
+	       &clk_rst->sclk_brst_pol);		/* sclk = 300 MHz */
 
 	/* Change the oscillator drive strength (from U-Boot -- why?) */
 	clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK,
@@ -590,16 +559,10 @@ void clock_init(void)
 	clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK);
 
 	/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
-	write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT |
-		 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT |
-		(CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT |
-		 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
-		&clk_rst->pllp_outa);
-	write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT |
-		 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT |
-		(CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT |
-		 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
-		&clk_rst->pllp_outb);
+	writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
+	       &clk_rst->pllp_outa);
+	writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
+	       &clk_rst->pllp_outb);
 
 	/* init pllx */
 	init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc,
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
index 0a3cb48641..9418e152da 100644
--- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
@@ -282,17 +282,17 @@ inline static void write32(uint32_t val, void *addr)
 
 inline static void setbits32(uint32_t bits, void *addr)
 {
-	write32(read32(addr) | bits, addr);
+	writel(read32(addr) | bits, addr);
 }
 
 inline static void clrbits32(uint32_t bits, void *addr)
 {
-	write32(read32(addr) & ~bits, addr);
+	writel(read32(addr) & ~bits, addr);
 }
 
 static void __attribute__((noreturn)) reset(void)
 {
-	write32(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
+	writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
 	halt();
 }
 
@@ -337,7 +337,7 @@ static void config_oscillator(void)
 	osc_ctrl &= ~OSC_XOFS_MASK;
 	osc_ctrl |= (xofs << OSC_XOFS_SHIFT);
 	osc_ctrl |= OSC_XOE;
-	write32(osc_ctrl, clk_rst_osc_ctrl_ptr);
+	writel(osc_ctrl, clk_rst_osc_ctrl_ptr);
 }
 
 static void config_pllu(void)
@@ -382,17 +382,17 @@ static void config_pllu(void)
 	// Configure PLLU.
 	uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE |
 			(divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT);
-	write32(base, clk_rst_pllu_base_ptr);
+	writel(base, clk_rst_pllu_base_ptr);
 	uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) |
 			(lfcon << PLLU_LFCON_SHIFT);
-	write32(misc, clk_rst_pllu_misc_ptr);
+	writel(misc, clk_rst_pllu_misc_ptr);
 
 	// Enable PLLU.
 	base &= ~PLLU_BYPASS;
 	base |= PLLU_ENABLE;
-	write32(base, clk_rst_pllu_base_ptr);
+	writel(base, clk_rst_pllu_base_ptr);
 	misc |= PLLU_LOCK_ENABLE;
-	write32(misc, clk_rst_pllu_misc_ptr);
+	writel(misc, clk_rst_pllu_misc_ptr);
 }
 
 static void config_tsc(void)
@@ -400,26 +400,26 @@ static void config_tsc(void)
 	// Tell the TSC the oscillator frequency.
 	switch (get_osc_freq()) {
 	case OSC_FREQ_12:
-		write32(12000000, sysctr_cntfid0_ptr);
+		writel(12000000, sysctr_cntfid0_ptr);
 		break;
 	case OSC_FREQ_48:
-		write32(48000000, sysctr_cntfid0_ptr);
+		writel(48000000, sysctr_cntfid0_ptr);
 		break;
 	case OSC_FREQ_16P8:
-		write32(16800000, sysctr_cntfid0_ptr);
+		writel(16800000, sysctr_cntfid0_ptr);
 		break;
 	case OSC_FREQ_19P2:
-		write32(19200000, sysctr_cntfid0_ptr);
+		writel(19200000, sysctr_cntfid0_ptr);
 		break;
 	case OSC_FREQ_38P4:
-		write32(38400000, sysctr_cntfid0_ptr);
+		writel(38400000, sysctr_cntfid0_ptr);
 		break;
 	case OSC_FREQ_26:
-		write32(26000000, sysctr_cntfid0_ptr);
+		writel(26000000, sysctr_cntfid0_ptr);
 		break;
 	default:
 		// Default to 13MHz.
-		write32(13000000, sysctr_cntfid0_ptr);
+		writel(13000000, sysctr_cntfid0_ptr);
 		break;
 	}
 
@@ -430,8 +430,8 @@ static void config_tsc(void)
 static void enable_cpu_clocks(void)
 {
 	// Enable the CPU complex clock.
-	write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
-	write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
+	writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
+	writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
 }
 
 
@@ -441,7 +441,7 @@ static void enable_cpu_clocks(void)
 static void config_core_sight(void)
 {
 	// Enable the CoreSight clock.
-	write32(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
+	writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
 
 	/*
 	 * De-assert CoreSight reset.
@@ -449,22 +449,22 @@ static void config_core_sight(void)
 	 *       now. It will be restored to its original clock source
 	 *       when the CPU-side restoration code runs.
 	 */
-	write32(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
+	writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
 }
 
 static void config_mselect(void)
 {
 	// Set MSELECT clock source to PLLP with 1:4 divider.
-	write32((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0,
-		clk_rst_clk_src_mselect_ptr);
+	writel((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0,
+	       clk_rst_clk_src_mselect_ptr);
 
 	// Enable clock to MSELECT.
-	write32(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr);
+	writel(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr);
 
 	udelay(2);
 
 	// Bring MSELECT out of reset.
-	write32(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr);
+	writel(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr);
 }
 
 
@@ -474,19 +474,16 @@ static void config_mselect(void)
 static void clear_cpu_resets(void)
 {
 	// Take the non-cpu of the G and LP clusters out of reset.
-	write32(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr);
-	write32(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr);
+	writel(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr);
+	writel(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr);
 
 	// Clear software controlled reset of the slow cluster.
-	write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
-		clk_rst_rst_cpulp_cmplx_clr_ptr);
+	writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
+	       clk_rst_rst_cpulp_cmplx_clr_ptr);
 
 	// Clear software controlled reset of the fast cluster.
-	write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
-		CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
-		CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
-		CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3,
-		clk_rst_rst_cpug_cmplx_clr_ptr);
+	writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3,
+	       clk_rst_rst_cpug_cmplx_clr_ptr);
 }
 
 
@@ -516,7 +513,7 @@ static void power_on_partition(unsigned id)
 	uint32_t bit = 0x1 << id;
 	if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) {
 		// Partition is not on. Turn it on.
-		write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
+		writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
 
 		// Wait until the partition is powerd on.
 		while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit))
@@ -546,8 +543,8 @@ static void power_on_main_cpu(void)
 	 */
 	uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr);
 
-	write32(orig_timer * (204000000 / 32768),
-		pmc_ctlr_cpupwrgood_timer_ptr);
+	writel(orig_timer * (204000000 / 32768),
+	       pmc_ctlr_cpupwrgood_timer_ptr);
 
 	if (wakeup_on_lp()) {
 		power_on_partition(PARTID_C1NC);
@@ -559,7 +556,7 @@ static void power_on_main_cpu(void)
 	}
 
 	// Restore the original PMC_CPUPWRGOOD_TIMER.
-	write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
+	writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
 }
 
 
@@ -581,17 +578,17 @@ void lp0_resume(void)
 			  flow_ctlr_cluster_control_ptr);
 
 	// Program SUPER_CCLK_DIVIDER.
-	write32(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
+	writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
 
 	config_core_sight();
 
 	config_pllu();
 
 	// Set the CPU reset vector.
-	write32(get_wakeup_vector(), evp_cpu_reset_ptr);
+	writel(get_wakeup_vector(), evp_cpu_reset_ptr);
 
 	// Select CPU complex clock source.
-	write32(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
+	writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
 
 	config_mselect();
 
@@ -602,14 +599,14 @@ void lp0_resume(void)
 	uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr);
 	ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
 	ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT;
-	write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
+	writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
 
 	config_tsc();
 
 	// Disable VPR.
-	write32(0, mc_video_protect_size_mb_ptr);
-	write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
-		mc_video_protect_reg_ctrl_ptr);
+	writel(0, mc_video_protect_size_mb_ptr);
+	writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
+               mc_video_protect_reg_ctrl_ptr);
 
 	enable_cpu_clocks();
 
@@ -622,8 +619,8 @@ void lp0_resume(void)
 
 	// Halt the AVP.
 	while (1)
-		write32(FLOW_MODE_STOP | EVENT_JTAG,
-			flow_ctlr_halt_cop_events_ptr);
+		writel(FLOW_MODE_STOP | EVENT_JTAG,
+		       flow_ctlr_halt_cop_events_ptr);
 }
 
 
diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c
index 825b27bda9..b31d3a7781 100644
--- a/src/soc/nvidia/tegra124/power.c
+++ b/src/soc/nvidia/tegra124/power.c
@@ -48,7 +48,7 @@ static void power_ungate_partition(uint32_t id)
 		pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
 		pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
 		pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
-		write32(pwrgate_toggle, &pmc->pwrgate_toggle);
+		writel(pwrgate_toggle, &pmc->pwrgate_toggle);
 
 		// Wait for the request to be accepted.
 		while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)
@@ -73,12 +73,12 @@ void power_enable_and_ungate_cpu(void)
 	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (150MHz),
 	 * set it for 5ms as per SysEng (5ms * PCLK_KHZ * 1000 / 1s).
 	 */
-	write32((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer);
+	writel((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer);
 
 	uint32_t cntrl = read32(&pmc->cntrl);
 	cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY;
 	cntrl |= PMC_CNTRL_CPUPWRREQ_OE;
-	write32(cntrl, &pmc->cntrl);
+	writel(cntrl, &pmc->cntrl);
 
 	power_ungate_partition(POWER_PARTID_CRAIL);
 
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index aefb4da0d6..0584177d5e 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -230,7 +230,7 @@ int spi_claim_bus(struct spi_slave *slave)
 	else
 		val |= SPI_CMD1_CS_SW_VAL;
 
-	write32(val, &regs->command1);
+	writel(val, &regs->command1);
 	return 0;
 }
 
@@ -246,7 +246,7 @@ void spi_release_bus(struct spi_slave *slave)
 	else
 		val &= ~SPI_CMD1_CS_SW_VAL;
 
-	write32(val, &regs->command1);
+	writel(val, &regs->command1);
 }
 
 static void dump_fifo_status(struct tegra_spi_channel *spi)
@@ -383,12 +383,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi,
 
 	/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
 	 * PIO transfers */
-	write32(todo - 1, &spi->regs->dma_blk);
+	writel(todo - 1, &spi->regs->dma_blk);
 
 	if (dir == SPI_SEND) {
 		unsigned int to_fifo = bytes;
 		while (to_fifo) {
-			write32(*p, &spi->regs->tx_fifo);
+			writel(*p, &spi->regs->tx_fifo);
 			p++;
 			to_fifo--;
 		}
@@ -493,11 +493,11 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
 		/* ensure bytes to send will be visible to DMA controller */
 		dcache_clean_by_mva(spi->out_buf, bytes);
 
-		write32((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
-		write32((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
+		writel((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
+		writel((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
 		setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
 		setup_dma_params(spi, spi->dma_out);
-		write32(wcount, &spi->dma_out->regs->wcount);
+		writel(wcount, &spi->dma_out->regs->wcount);
 	} else {
 		spi->dma_in = dma_claim();
 		if (!spi->dma_in)
@@ -506,15 +506,15 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
 		/* avoid data collisions */
 		dcache_clean_invalidate_by_mva(spi->in_buf, bytes);
 
-		write32((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
-		write32((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
+		writel((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
+		writel((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
 		clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
 		setup_dma_params(spi, spi->dma_in);
-		write32(wcount, &spi->dma_in->regs->wcount);
+		writel(wcount, &spi->dma_in->regs->wcount);
 	}
 
 	/* BLOCK_SIZE starts at n-1 */
-	write32(todo - 1, &spi->regs->dma_blk);
+	writel(todo - 1, &spi->regs->dma_blk);
 	return todo;
 }
 
diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c
index a25540b025..26aec20030 100644
--- a/src/soc/nvidia/tegra124/uart.c
+++ b/src/soc/nvidia/tegra124/uart.c
@@ -56,20 +56,19 @@ static void tegra124_uart_init(struct tegra124_uart *uart_ptr)
 	tegra124_uart_tx_flush(uart_ptr);
 
 	// Disable interrupts.
-	write8(0, &uart_ptr->ier);
+	writeb(0, &uart_ptr->ier);
 	// Force DTR and RTS to high.
-	write8(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
+	writeb(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
 	// Set line configuration, access divisor latches.
-	write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
+	writeb(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
 	// Set the divisor.
-	write8(divisor & 0xff, &uart_ptr->dll);
-	write8((divisor >> 8) & 0xff, &uart_ptr->dlm);
+	writeb(divisor & 0xff, &uart_ptr->dll);
+	writeb((divisor >> 8) & 0xff, &uart_ptr->dlm);
 	// Hide the divisor latches.
-	write8(line_config, &uart_ptr->lcr);
+	writeb(line_config, &uart_ptr->lcr);
 	// Enable FIFOs, and clear receive and transmit.
-	write8(UART8250_FCR_FIFO_EN |
-		UART8250_FCR_CLEAR_RCVR |
-		UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
+	writeb(UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT,
+	       &uart_ptr->fcr);
 }
 
 static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr)
@@ -82,7 +81,7 @@ static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr)
 static void tegra124_uart_tx_byte(struct tegra124_uart *uart_ptr, unsigned char data)
 {
 	while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
-	write8(data, &uart_ptr->thr);
+	writeb(data, &uart_ptr->thr);
 }
 
 static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr)
diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c
index 72563f5095..377d083e02 100644
--- a/src/soc/nvidia/tegra132/addressmap.c
+++ b/src/soc/nvidia/tegra132/addressmap.c
@@ -187,9 +187,9 @@ void trustzone_region_init(void)
 		return;
 
 	/* Set the carveout region. */
-	write32(tz_base_mib << 20, &mc->security_cfg0);
-	write32(tz_size_mib, &mc->security_cfg1);
+	writel(tz_base_mib << 20, &mc->security_cfg0);
+	writel(tz_size_mib, &mc->security_cfg1);
 
 	/* Enable SMMU translations */
-	write32(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config);
+	writel(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config);
 }
diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c
index ede46ef401..6fd36eb2bd 100644
--- a/src/soc/nvidia/tegra132/bootblock.c
+++ b/src/soc/nvidia/tegra132/bootblock.c
@@ -46,7 +46,7 @@ static void save_odmdata(void)
 	bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT));
 	if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) {
 		odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT));
-		write32(odmdata, &pmc->odmdata);
+		writel(odmdata, &pmc->odmdata);
 	}
 }
 
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index 520c244fbf..1cc59add84 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -46,12 +46,12 @@ static int ccplex_start(void)
 	struct tegra_pmc_regs * const pmc = PMC_REGS;
 
 	/* Set the handshake bit to be knocked down. */
-	write32(handshake_mask, &pmc->scratch118);
+	writel(handshake_mask, &pmc->scratch118);
 
 	/* Assert nCXRSET[1] */
 	reg = read32(CLK_RST_REG(rst_cpu_cmplx_set));
 	reg |= cxreset1_mask;
-	write32(reg, CLK_RST_REG(rst_cpu_cmplx_set));
+	writel(reg, CLK_RST_REG(rst_cpu_cmplx_set));
 
 	stopwatch_init_msecs_expire(&sw, timeout_ms);
 	while (1) {
@@ -140,14 +140,14 @@ static void request_ram_repair(void)
 	/* Perform cluster 0 ram repair */
 	reg = read32(&flow->ram_repair);
 	reg |= req;
-	write32(reg, &flow->ram_repair);
+	writel(reg, &flow->ram_repair);
 	while ((read32(&flow->ram_repair) & sts) != sts)
 		;
 
 	/* Perform cluster 1 ram repair */
 	reg = read32(&flow->ram_repair_cluster1);
 	reg |= req;
-	write32(reg, &flow->ram_repair_cluster1);
+	writel(reg, &flow->ram_repair_cluster1);
 	while ((read32(&flow->ram_repair_cluster1) & sts) != sts)
 		;
 
@@ -169,11 +169,11 @@ void ccplex_cpu_prepare(void)
 static void start_common_clocks(void)
 {
 	/* Clear fast CPU partition reset. */
-	write32(CRC_RST_CPUG_CLR_NONCPU, CLK_RST_REG(rst_cpug_cmplx_clr));
+	writel(CRC_RST_CPUG_CLR_NONCPU, CLK_RST_REG(rst_cpug_cmplx_clr));
 
 	/* Clear reset of L2 and CoreSight components. */
-	write32(CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
-		CLK_RST_REG(rst_cpug_cmplx_clr));
+	writel(CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
+	       CLK_RST_REG(rst_cpug_cmplx_clr));
 }
 
 void ccplex_cpu_start(void *entry_addr)
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c
index 661d38a55d..4cd8a5886d 100644
--- a/src/soc/nvidia/tegra132/clock.c
+++ b/src/soc/nvidia/tegra132/clock.c
@@ -186,11 +186,11 @@ void clock_init_arm_generic_timer(void)
 	set_cntfrq(freq);
 
 	/* Record the system timer frequency. */
-	write32(freq, &sysctr->cntfid0);
+	writel(freq, &sysctr->cntfid0);
 	/* Enable the system counter. */
 	uint32_t cntcr = read32(&sysctr->cntcr);
 	cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG;
-	write32(cntcr, &sysctr->cntcr);
+	writel(cntcr, &sysctr->cntcr);
 }
 
 #define SOR0_CLK_SEL0			(1 << 14)
@@ -243,25 +243,14 @@ static void init_utmip_pll(void)
 	clrbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */
 	udelay(1);
 
-	write32(80 << 16 |			/* (rst) phy_divn */
-		1 << 8 |			/* (rst) phy_divm */
-		0, CLK_RST_REG(utmip_pll_cfg0));/* 960MHz * 1 / 80 == 12 MHz */
+	writel(80 << 16 | 1 << 8 | 0, CLK_RST_REG(utmip_pll_cfg0));/* 960MHz * 1 / 80 == 12 MHz */
 
-	write32(div_round_up(khz, 8000) << 27 |	/* pllu_enbl_cnt / 8 (1us) */
-		0 << 16 |			/* PLLU pwrdn */
-		0 << 14 |			/* pll_enable pwrdn */
-		0 << 12 |			/* pll_active pwrdn */
-		div_round_up(khz, 102) << 0 |	/* phy_stbl_cnt / 256 (2.5ms) */
-		0, CLK_RST_REG(utmip_pll_cfg1));
+	writel(div_round_up(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | div_round_up(khz, 102) << 0 | 0,
+	       CLK_RST_REG(utmip_pll_cfg1));
 
 	/* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */
-	write32(0 << 24 |			/* SAMP_D/XDEV pwrdn */
-		div_round_up(khz, 3200) << 18 |	/* phy_actv_cnt / 16 (5us) */
-		div_round_up(khz, 256) << 6 |	/* pllu_stbl_cnt / 256 (1ms) */
-		0 << 4 |			/* SAMP_C/USB3 pwrdn */
-		0 << 2 |			/* SAMP_B/XHOST pwrdn */
-		0 << 0 |			/* SAMP_A/USBD pwrdn */
-		0, CLK_RST_REG(utmip_pll_cfg2));
+	writel(0 << 24 | div_round_up(khz, 3200) << 18 | div_round_up(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0,
+	       CLK_RST_REG(utmip_pll_cfg2));
 
 	setbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */
 }
@@ -398,9 +387,8 @@ u32 clock_configure_plld(u32 frequency)
  * been determined through trial and error (must lead to div 13 at 24MHz). */
 void clock_early_uart(void)
 {
-	write32(CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT |
-		CLK_UART_DIV_OVERRIDE |
-		CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), CLK_RST_REG(clk_src_uarta));
+	writel(CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900),
+	       CLK_RST_REG(clk_src_uarta));
 
 	clock_enable_clear_reset_l(CLK_L_UARTA);
 }
@@ -503,8 +491,8 @@ void clock_cpu0_config(void)
 	 */
 	do {
 		if (readl(&clst_clk->misc_ctrl) & CLK_SWITCH_MATCH) {
-			write32((CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28),
-				&clst_clk->cclk_brst_pol);
+			writel((CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28),
+			       &clst_clk->cclk_brst_pol);
 			break;
 		}
 
@@ -524,9 +512,8 @@ void clock_cpu0_config(void)
 void clock_halt_avp(void)
 {
 	for (;;)
-		write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ |
-			FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
-			&flow->halt_cop_events);
+		writel(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
+		       &flow->halt_cop_events);
 }
 
 void clock_init(void)
@@ -542,13 +529,12 @@ void clock_init(void)
 
 	/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
 	 * features section in the TRM). */
-	write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
-		CLK_RST_REG(clk_sys_rate));	/* pclk = hclk = sclk/2 */
-	write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT |
-		PLL_OUT_CLKEN | PLL_OUT_RSTN, CLK_RST_REG(pllc_out));
-	write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT |
-		SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
-		CLK_RST_REG(sclk_brst_pol));		/* sclk = 300 MHz */
+	writel(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
+	       CLK_RST_REG(clk_sys_rate));	/* pclk = hclk = sclk/2 */
+	writel(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN,
+	       CLK_RST_REG(pllc_out));
+	writel(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
+	       CLK_RST_REG(sclk_brst_pol));		/* sclk = 300 MHz */
 
 	/* Change the oscillator drive strength (from U-Boot -- why?) */
 	clrsetbits_le32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK,
@@ -563,16 +549,10 @@ void clock_init(void)
 			OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
 
 	/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
-	write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT |
-		 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT |
-		(CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT |
-		 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
-		CLK_RST_REG(pllp_outa));
-	write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT |
-		 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT |
-		(CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT |
-		 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
-		CLK_RST_REG(pllp_outb));
+	writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
+	       CLK_RST_REG(pllp_outa));
+	writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
+	       CLK_RST_REG(pllp_outb));
 
 	/* init pllu */
 	init_pll(CLK_RST_REG(pllu_base), CLK_RST_REG(pllu_misc),
diff --git a/src/soc/nvidia/tegra132/cpu.c b/src/soc/nvidia/tegra132/cpu.c
index c79bc9cf4e..8cd2c0faea 100644
--- a/src/soc/nvidia/tegra132/cpu.c
+++ b/src/soc/nvidia/tegra132/cpu.c
@@ -40,15 +40,15 @@ static void enable_core_clocks(int cpu)
 
 	/* Clear reset of CPU components. */
 	if (cpu == 0)
-		write32(cpu0_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
+		writel(cpu0_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
 	else
-		write32(cpu1_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
+		writel(cpu1_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
 }
 
 static void set_armv8_32bit_reset_vector(uintptr_t entry)
 {
 	void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR;
-	write32(entry, evp_cpu_reset_vector);
+	writel(entry, evp_cpu_reset_vector);
 }
 
 static void set_armv8_64bit_reset_vector(uintptr_t entry)
@@ -56,8 +56,8 @@ static void set_armv8_64bit_reset_vector(uintptr_t entry)
 	struct tegra_pmc_regs * const pmc = PMC_REGS;
 
 	/* Currently assume 32-bit addresses only. */
-	write32(entry, &pmc->secure_scratch34);
-	write32(0, &pmc->secure_scratch35);
+	writel(entry, &pmc->secure_scratch34);
+	writel(0, &pmc->secure_scratch35);
 }
 
 void cpu_prepare_startup(void *entry_64)
diff --git a/src/soc/nvidia/tegra132/dsi.c b/src/soc/nvidia/tegra132/dsi.c
index 188792bd2c..8508b6666d 100644
--- a/src/soc/nvidia/tegra132/dsi.c
+++ b/src/soc/nvidia/tegra132/dsi.c
@@ -869,7 +869,7 @@ static int dsi_enable(struct soc_nvidia_tegra132_config *config)
 	tegra_output_dsi_setup_clock(dsi_a, config);
 
 	/* configure APB_MISC_GP_MIPI_PAD_CTRL_0 */
-	write32(DSIB_MODE_DSI, (unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0);
+	writel(DSIB_MODE_DSI, (unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0);
 
 	/* configure phy interface timing registers */
 	tegra_dsi_set_phy_timing(dsi_a);
diff --git a/src/soc/nvidia/tegra132/flow_ctrl.c b/src/soc/nvidia/tegra132/flow_ctrl.c
index 4da54b1ea1..6d7d11590c 100644
--- a/src/soc/nvidia/tegra132/flow_ctrl.c
+++ b/src/soc/nvidia/tegra132/flow_ctrl.c
@@ -62,7 +62,7 @@ static uint32_t flowctrl_read_cpu_csr(int cpu)
 
 static void flowctrl_write_cpu_csr(int cpu, uint32_t val)
 {
-	write32(val, tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
+	writel(val, tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
 	val = readl(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
 }
 
diff --git a/src/soc/nvidia/tegra132/i2c6.c b/src/soc/nvidia/tegra132/i2c6.c
index 73a98562ad..ef86126935 100644
--- a/src/soc/nvidia/tegra132/i2c6.c
+++ b/src/soc/nvidia/tegra132/i2c6.c
@@ -43,7 +43,7 @@ static void remove_clamps(int id)
 		return;
 
 	/* Remove clamp */
-	write32((1 << id), &pmc->remove_clamping_cmd);
+	writel((1 << id), &pmc->remove_clamping_cmd);
 
 	/* Wait for clamp off */
 	while (partition_clamp_on(id))
@@ -86,7 +86,7 @@ void soc_configure_i2c6pad(void)
 	soc_configure_host1x();
 
 	/* Now we can write the I2C6 mux in DPAUX */
-	write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
+	writel(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
 
 	/*
 	 * Delay before turning off Host1X/DPAUX clocks.
diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
index a52e918ee0..29fb9dedd6 100644
--- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
@@ -261,17 +261,17 @@ inline static void write32(uint32_t val, void *addr)
 
 inline static void setbits32(uint32_t bits, void *addr)
 {
-	write32(read32(addr) | bits, addr);
+	writel(read32(addr) | bits, addr);
 }
 
 inline static void clrbits32(uint32_t bits, void *addr)
 {
-	write32(read32(addr) & ~bits, addr);
+	writel(read32(addr) & ~bits, addr);
 }
 
 static void __attribute__((noreturn)) reset(void)
 {
-	write32(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
+	writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
 	halt();
 }
 
@@ -370,18 +370,18 @@ static void enable_uart(void)
 	clrbits32(uart_mask, uart_rst_reg);
 
 	/* Program UART clock source: PLLP (408000000) */
-	write32(0, uart_clk_source);
+	writel(0, uart_clk_source);
 
 	/* Program 115200n8 to the uart port */
 	/* baud-rate of 115200 */
-	write32(LCR_DLAB, (uart_base + UART_LCR));
-	write32((UART_RATE_115200 & 0xff), (uart_base + UART_THR_DLAB));
-	write32((UART_RATE_115200 >> 8), (uart_base + UART_IER_DLAB));
+	writel(LCR_DLAB, (uart_base + UART_LCR));
+	writel((UART_RATE_115200 & 0xff), (uart_base + UART_THR_DLAB));
+	writel((UART_RATE_115200 >> 8), (uart_base + UART_IER_DLAB));
 	/* 8-bit and no parity */
-	write32(LCR_WD_SIZE_8, (uart_base + UART_LCR));
+	writel(LCR_WD_SIZE_8, (uart_base + UART_LCR));
 	/* enable and clear RX/TX FIFO */
-	write32((FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO),
-		(uart_base + UART_IIR_FCR));
+	writel((FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO),
+	       (uart_base + UART_IIR_FCR));
 }
 
 /* Accessors. */
@@ -401,7 +401,7 @@ static unsigned get_osc_freq(void)
 
 static void enable_jtag(void)
 {
-	write32(PP_CONFIG_CTL_JTAG, misc_pp_config_ctl_ptr);
+	writel(PP_CONFIG_CTL_JTAG, misc_pp_config_ctl_ptr);
 }
 
 /* Clock configuration. */
@@ -417,7 +417,7 @@ static void config_oscillator(void)
 	osc_ctrl &= ~OSC_XOFS_MASK;
 	osc_ctrl |= (xofs << OSC_XOFS_SHIFT);
 	osc_ctrl |= OSC_XOE;
-	write32(osc_ctrl, clk_rst_osc_ctrl_ptr);
+	writel(osc_ctrl, clk_rst_osc_ctrl_ptr);
 }
 
 static void config_pllu(void)
@@ -462,24 +462,24 @@ static void config_pllu(void)
 	// Configure PLLU.
 	uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE |
 			(divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT);
-	write32(base, clk_rst_pllu_base_ptr);
+	writel(base, clk_rst_pllu_base_ptr);
 	uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) |
 			(lfcon << PLLU_LFCON_SHIFT);
-	write32(misc, clk_rst_pllu_misc_ptr);
+	writel(misc, clk_rst_pllu_misc_ptr);
 
 	// Enable PLLU.
 	base &= ~PLLU_BYPASS;
 	base |= PLLU_ENABLE;
-	write32(base, clk_rst_pllu_base_ptr);
+	writel(base, clk_rst_pllu_base_ptr);
 	misc |= PLLU_LOCK_ENABLE;
-	write32(misc, clk_rst_pllu_misc_ptr);
+	writel(misc, clk_rst_pllu_misc_ptr);
 }
 
 static void enable_cpu_clocks(void)
 {
 	// Enable the CPU complex clock.
-	write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
-	write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
+	writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
+	writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
 }
 
 
@@ -489,7 +489,7 @@ static void enable_cpu_clocks(void)
 static void config_core_sight(void)
 {
 	// Enable the CoreSight clock.
-	write32(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
+	writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
 
 	/*
 	 * De-assert CoreSight reset.
@@ -497,7 +497,7 @@ static void config_core_sight(void)
 	 *       now. It will be restored to its original clock source
 	 *       when the CPU-side restoration code runs.
 	 */
-	write32(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
+	writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
 }
 
 
@@ -508,11 +508,11 @@ static void clear_cpu_resets(void)
 	/* Hold CPU1 in reset */
 	setbits32(SET_CXRESET1, clk_rst_rst_cpulp_cmplx_set_ptr);
 
-	write32(CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG,
-		clk_rst_rst_cpug_cmplx_clr_ptr);
+	writel(CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG,
+	       clk_rst_rst_cpug_cmplx_clr_ptr);
 
-	write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
-		clk_rst_rst_cpug_cmplx_clr_ptr);
+	writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
+	       clk_rst_rst_cpug_cmplx_clr_ptr);
 }
 
 
@@ -542,7 +542,7 @@ static void power_on_partition(unsigned id)
 	uint32_t bit = 0x1 << id;
 	if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) {
 		// Partition is not on. Turn it on.
-		write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
+		writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
 
 		// Wait until the partition is powerd on.
 		while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit))
@@ -572,15 +572,15 @@ static void power_on_main_cpu(void)
 	 */
 	uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr);
 
-	write32(orig_timer * (204000000 / 32768),
-		pmc_ctlr_cpupwrgood_timer_ptr);
+	writel(orig_timer * (204000000 / 32768),
+	       pmc_ctlr_cpupwrgood_timer_ptr);
 
 	power_on_partition(PARTID_CRAIL);
 	power_on_partition(PARTID_C0NC);
 	power_on_partition(PARTID_CE0);
 
 	// Restore the original PMC_CPUPWRGOOD_TIMER.
-	write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
+	writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
 }
 
 
@@ -609,7 +609,7 @@ void lp0_resume(void)
 	config_oscillator();
 
 	// Program SUPER_CCLK_DIVIDER.
-	write32(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
+	writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
 
 	config_core_sight();
 
@@ -623,12 +623,12 @@ void lp0_resume(void)
 	 * T132 always resets to AARCH32 and SW needs to write RMR_EL3
 	 * to bootstrap into AARCH64.
 	 */
-	write32(get_wakeup_vector(), pmc_ctlr_secure_scratch34_ptr);
-	write32(0, pmc_ctlr_secure_scratch35_ptr);
-	write32((uint32_t)aarch64_trampoline, evp_cpu_reset_ptr);
+	writel(get_wakeup_vector(), pmc_ctlr_secure_scratch34_ptr);
+	writel(0, pmc_ctlr_secure_scratch35_ptr);
+	writel((uint32_t)aarch64_trampoline, evp_cpu_reset_ptr);
 
 	// Select CPU complex clock source.
-	write32(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
+	writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
 
 	// Disable PLLX since it isn't used as CPU clock source.
 	clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr);
@@ -637,12 +637,12 @@ void lp0_resume(void)
 	uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr);
 	ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
 	ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT;
-	write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
+	writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
 
 	// Disable VPR.
-	write32(0, mc_video_protect_size_mb_ptr);
-	write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
-		mc_video_protect_reg_ctrl_ptr);
+	writel(0, mc_video_protect_size_mb_ptr);
+	writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
+               mc_video_protect_reg_ctrl_ptr);
 
 	enable_cpu_clocks();
 
@@ -655,8 +655,8 @@ void lp0_resume(void)
 
 	// Halt the AVP.
 	while (1)
-		write32(FLOW_MODE_STOP | EVENT_JTAG,
-			flow_ctlr_halt_cop_events_ptr);
+		writel(FLOW_MODE_STOP | EVENT_JTAG,
+		       flow_ctlr_halt_cop_events_ptr);
 }
 
 
diff --git a/src/soc/nvidia/tegra132/padconfig.c b/src/soc/nvidia/tegra132/padconfig.c
index 5f7f2e4f93..790f10f9c0 100644
--- a/src/soc/nvidia/tegra132/padconfig.c
+++ b/src/soc/nvidia/tegra132/padconfig.c
@@ -36,7 +36,7 @@ static inline uint32_t pad_get_pinmux(int index)
 
 static inline void pad_set_pinmux(int index, uint32_t reg)
 {
-	return write32(reg, &pinmux_regs[index]);
+	return writel(reg, &pinmux_regs[index]);
 }
 
 static inline void pad_set_gpio_out(int gpio_index, int val)
@@ -45,10 +45,10 @@ static inline void pad_set_gpio_out(int gpio_index, int val)
 	int port = gpio_index_to_port(gpio_index);
 	int bit = gpio_to_bit(gpio_index);
 
-	write32((1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit),
-		&regs->out_value_mask[port]);
-	write32((1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit),
-		&regs->out_enable_mask[port]);
+	writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit),
+	       &regs->out_value_mask[port]);
+	writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit),
+	       &regs->out_enable_mask[port]);
 }
 
 static inline void pad_set_mode(int gpio_index, int sfio_or_gpio)
@@ -57,8 +57,8 @@ static inline void pad_set_mode(int gpio_index, int sfio_or_gpio)
 	int port = gpio_index_to_port(gpio_index);
 	int bit = gpio_to_bit(gpio_index);
 
-	write32((1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit),
-		&regs->config_mask[port]);
+	writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit),
+	       &regs->config_mask[port]);
 }
 
 static inline void pad_set_gpio_mode(int gpio_index)
diff --git a/src/soc/nvidia/tegra132/power.c b/src/soc/nvidia/tegra132/power.c
index 4316d763db..0ebfd7c53e 100644
--- a/src/soc/nvidia/tegra132/power.c
+++ b/src/soc/nvidia/tegra132/power.c
@@ -41,7 +41,7 @@ void power_ungate_partition(uint32_t id)
 		pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
 		pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
 		pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
-		write32(pwrgate_toggle, &pmc->pwrgate_toggle);
+		writel(pwrgate_toggle, &pmc->pwrgate_toggle);
 
 		/* Wait for the request to be accepted. */
 		while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index 476dec7a03..7923f7e3cd 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -83,9 +83,9 @@ static void lock_down_vpr(void)
 {
 	struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE;
 
-	write32(0, &regs->video_protect_bom);
-	write32(0, &regs->video_protect_size_mb);
-	write32(1, &regs->video_protect_reg_ctrl);
+	writel(0, &regs->video_protect_bom);
+	writel(0, &regs->video_protect_size_mb);
+	writel(1, &regs->video_protect_reg_ctrl);
 }
 
 static void soc_init(device_t dev)
diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c
index 0bff31a245..e240700f06 100644
--- a/src/soc/nvidia/tegra132/spi.c
+++ b/src/soc/nvidia/tegra132/spi.c
@@ -230,7 +230,7 @@ int spi_claim_bus(struct spi_slave *slave)
 	else
 		val |= SPI_CMD1_CS_SW_VAL;
 
-	write32(val, &regs->command1);
+	writel(val, &regs->command1);
 	return 0;
 }
 
@@ -246,7 +246,7 @@ void spi_release_bus(struct spi_slave *slave)
 	else
 		val &= ~SPI_CMD1_CS_SW_VAL;
 
-	write32(val, &regs->command1);
+	writel(val, &regs->command1);
 }
 
 static void dump_fifo_status(struct tegra_spi_channel *spi)
@@ -383,12 +383,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi,
 
 	/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
 	 * PIO transfers */
-	write32(todo - 1, &spi->regs->dma_blk);
+	writel(todo - 1, &spi->regs->dma_blk);
 
 	if (dir == SPI_SEND) {
 		unsigned int to_fifo = bytes;
 		while (to_fifo) {
-			write32(*p, &spi->regs->tx_fifo);
+			writel(*p, &spi->regs->tx_fifo);
 			p++;
 			to_fifo--;
 		}
@@ -493,11 +493,12 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
 		/* ensure bytes to send will be visible to DMA controller */
 		dcache_clean_by_mva(spi->out_buf, bytes);
 
-		write32((uintptr_t)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
-		write32((uintptr_t)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
+		writel((uintptr_t) & spi->regs->tx_fifo,
+		       &spi->dma_out->regs->apb_ptr);
+		writel((uintptr_t)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
 		setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
 		setup_dma_params(spi, spi->dma_out);
-		write32(wcount, &spi->dma_out->regs->wcount);
+		writel(wcount, &spi->dma_out->regs->wcount);
 	} else {
 		spi->dma_in = dma_claim();
 		if (!spi->dma_in)
@@ -506,15 +507,16 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
 		/* avoid data collisions */
 		dcache_clean_invalidate_by_mva(spi->in_buf, bytes);
 
-		write32((uintptr_t)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
-		write32((uintptr_t)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
+		writel((uintptr_t)&spi->regs->rx_fifo,
+		       &spi->dma_in->regs->apb_ptr);
+		writel((uintptr_t)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
 		clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
 		setup_dma_params(spi, spi->dma_in);
-		write32(wcount, &spi->dma_in->regs->wcount);
+		writel(wcount, &spi->dma_in->regs->wcount);
 	}
 
 	/* BLOCK_SIZE starts at n-1 */
-	write32(todo - 1, &spi->regs->dma_blk);
+	writel(todo - 1, &spi->regs->dma_blk);
 	return todo;
 }
 
diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c
index 3a9ac22584..90765e1496 100644
--- a/src/soc/nvidia/tegra132/uart.c
+++ b/src/soc/nvidia/tegra132/uart.c
@@ -63,20 +63,19 @@ static void tegra132_uart_init(struct tegra132_uart *uart_ptr)
 	tegra132_uart_tx_flush(uart_ptr);
 
 	// Disable interrupts.
-	write8(0, &uart_ptr->ier);
+	writeb(0, &uart_ptr->ier);
 	// Force DTR and RTS to high.
-	write8(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
+	writeb(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
 	// Set line configuration, access divisor latches.
-	write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
+	writeb(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
 	// Set the divisor.
-	write8(divisor & 0xff, &uart_ptr->dll);
-	write8((divisor >> 8) & 0xff, &uart_ptr->dlm);
+	writeb(divisor & 0xff, &uart_ptr->dll);
+	writeb((divisor >> 8) & 0xff, &uart_ptr->dlm);
 	// Hide the divisor latches.
-	write8(line_config, &uart_ptr->lcr);
+	writeb(line_config, &uart_ptr->lcr);
 	// Enable FIFOs, and clear receive and transmit.
-	write8(UART8250_FCR_FIFO_EN |
-		UART8250_FCR_CLEAR_RCVR |
-		UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
+	writeb(UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT,
+	       &uart_ptr->fcr);
 }
 
 static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr)
@@ -89,7 +88,7 @@ static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr)
 static void tegra132_uart_tx_byte(struct tegra132_uart *uart_ptr, unsigned char data)
 {
 	while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
-	write8(data, &uart_ptr->thr);
+	writeb(data, &uart_ptr->thr);
 }
 
 static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr)