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authorChris Wang <chris.wang@amd.corp-partner.google.com>2020-12-23 04:42:26 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-01-25 09:11:17 +0000
commit5e0db41602d7e1550d6f669e65dcceb91c291e65 (patch)
tree19452901c68d3a379e69390784d5960937d3c279 /src/soc/nvidia
parent3ec3cb82f9ad5d71d19bc461177cca19f9ec6a59 (diff)
mb/google/zork: adjust the eDP panel power sequence
set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight on and vary backlight. BUG=b:171269338 BRANCH=zork TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on dalboz Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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