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| author | Bora Guvendik <bora.guvendik@intel.com> | 2020-11-16 11:23:48 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:34:44 +0000 |
| commit | 2a70419e7c9523cc9c40303bd3355e24b01ea603 (patch) | |
| tree | 7e3290a0badc28cb7d5f3aa8368ec8769b75d8a9 /src/soc/nvidia | |
| parent | c3c3e453ff4e6d73b52d88ab08a708610997f334 (diff) | |
soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and UART bars
BAR address used during early initilization of GPSI 2 is overlapping with UART bar.
//For GSPI2 this is the address calculated
GSPI_BUS_BASE(0xFE030000,2)=0xFE032000
GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)
//overlaps with
CONSOLE_UART_BASE_ADDRESS -> 0xfe032000
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3249a91df8a2e319aff6303ef9400e74163afe93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/nvidia')
0 files changed, 0 insertions, 0 deletions