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authorTim Crawford <tcrawford@system76.com>2022-05-18 16:00:34 -0600
committerFelix Held <felix-coreboot@felixheld.de>2022-07-14 23:09:32 +0000
commit59e03ebf4cd5f4b1cbf5f6ff6281d372e519e6a6 (patch)
treefddc587ca9d916657b0736a7e2fb86e61bead081 /src/soc/nvidia
parent44ef2123b05eb4f5f8d5578f1b0b2fd70d9507a9 (diff)
mb/system76: TGL-U: Disable AER for CPU PCIe RP
Disable PCIe Advanced Error Reporting on the CPU root port to prevent some SSDs from timing out on S0ix suspend. AER results in the drive not being able to switch from D3 back to D0. nvme 0000:01:00.0: can't change power state from D3cold to D0 (config space inaccessible) Known to affect at least the following SSD models: - ADATA XPG SX8200 Pro - Samsung 970 EVO Plus (FW version: 2B7QCXE7) Change-Id: I79da6b08ef1949f3bf1c6111aaa7e658bd29c0e2 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64080 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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