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authorSubrata Banik <subrata.banik@intel.com>2020-11-21 19:30:57 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-11-23 03:37:04 +0000
commit191bd827344302561c2aa900e5e5ecdd088c5888 (patch)
tree41dfe857cda70f1a4b8cbf455b962cf730d6e2e5 /src/soc/nvidia
parent6de5bf669850efb214fb30feb2bc07460baa5c91 (diff)
soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE
According to the latest Alderlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 512KiB. Change DCACHE_RAM_SIZE and DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). TEST=Able to pass FSP-M MRC training on LPDDR5 SKU without any hang. Change-Id: Ic831ca9110a15fdb48ad31a7db396740811bf0f2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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