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authorPatrick Georgi <pgeorgi@chromium.org>2016-02-19 17:33:26 +0100
committerPatrick Georgi <pgeorgi@google.com>2016-02-21 12:26:05 +0100
commita7cac0c21d85e651caaab2af7f8f1a7263e8abb9 (patch)
tree24040626ebcc01f20efaeb06bc41650431fcbd84 /src/soc/nvidia
parentf92c3fb260e083d4548a4029548cf90675c6ec29 (diff)
soc/*: fix uart's regwidth specification in cbtables
coreboot passes information about the serial port implementation to payloads through a cbtables entry. We set the register width to 1 on most SoCs because that looked as good a default as any, but checking the uart structs they use, it's 4 for all of them. Change-Id: I9848f79737106dc32f864ca901c0bc48f489e6b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13746 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/nvidia')
-rw-r--r--src/soc/nvidia/tegra124/uart.c2
-rw-r--r--src/soc/nvidia/tegra132/uart.c2
-rw-r--r--src/soc/nvidia/tegra210/uart.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c
index 7fc8eb626d..1d4934b0a3 100644
--- a/src/soc/nvidia/tegra124/uart.c
+++ b/src/soc/nvidia/tegra124/uart.c
@@ -136,7 +136,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
- serial.regwidth = 1;
+ serial.regwidth = 4;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c
index 50569e03bf..a530e2dfa4 100644
--- a/src/soc/nvidia/tegra132/uart.c
+++ b/src/soc/nvidia/tegra132/uart.c
@@ -149,7 +149,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
- serial.regwidth = 1;
+ serial.regwidth = 4;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c
index 40ce6d26f1..1f16067049 100644
--- a/src/soc/nvidia/tegra210/uart.c
+++ b/src/soc/nvidia/tegra210/uart.c
@@ -123,7 +123,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS;
serial.baud = default_baudrate();
- serial.regwidth = 1;
+ serial.regwidth = 4;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);