diff options
| author | Martin Roth <martinroth@google.com> | 2016-01-05 20:58:58 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-01-07 22:57:02 +0100 |
| commit | 2ed0aa258f4bcbf978998ccd3a76f7b1c2d3d031 (patch) | |
| tree | 3bb7459dcae2b0fa15ed409b1f7d3fb5f77af127 /src/soc/nvidia | |
| parent | 2e0d9447db22183e2d3393d84e221e8bb1613d45 (diff) | |
Correct some common spelling mistakes
- occured -> occurred
- accomodate -> accommodate
- existant -> existent
- asssertion -> assertion
- manangement -> management
- cotroller -> controller
Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12850
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra124/clock.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/clock.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index de7b218e25..4c087b8539 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -389,7 +389,7 @@ clock_display(u32 frequency) /* Initialize the UART and put it on CLK_M so we can use it during clock_init(). * Will later move it to PLLP in clock_config(). The divisor must be very small - * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 + * to accommodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 * CLK_SOURCE divider to get more precision. (This might still not be enough for * some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1900 has * been determined through trial and error (must lead to div 13 at 24MHz). */ diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index 73b05e0925..0db120d8d2 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -389,7 +389,7 @@ u32 clock_configure_plld(u32 frequency) /* Initialize the UART and put it on CLK_M so we can use it during clock_init(). * Will later move it to PLLP in clock_config(). The divisor must be very small - * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 + * to accommodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 * CLK_SOURCE divider to get more precision. (This might still not be enough for * some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1900 has * been determined through trial and error (must lead to div 13 at 24MHz). */ |