diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-29 18:31:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 19:27:53 +0200 |
| commit | 038e7247dc9705ff2d47dd90ec9a807f6feb52ba (patch) | |
| tree | 8cca6a6db31d20a8e045ee5892e8f9cb8de43f8d /src/soc/nvidia/tegra210 | |
| parent | f9e7d1b0ca7282a0d51313a68f90e9298c0c46c6 (diff) | |
src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra210')
| -rw-r--r-- | src/soc/nvidia/tegra210/bootblock_asm.S | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/ccplex.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/sdram_param.h | 4 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/romstage.c | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/nvidia/tegra210/bootblock_asm.S b/src/soc/nvidia/tegra210/bootblock_asm.S index 857900a6eb..62554422db 100644 --- a/src/soc/nvidia/tegra210/bootblock_asm.S +++ b/src/soc/nvidia/tegra210/bootblock_asm.S @@ -30,7 +30,7 @@ ENTRY(_start) /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are * installed, but at least the problem will show up near the code that * causes it. diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c index a652b7624e..8759c73227 100644 --- a/src/soc/nvidia/tegra210/ccplex.c +++ b/src/soc/nvidia/tegra210/ccplex.c @@ -72,7 +72,7 @@ static void request_ram_repair(void) stopwatch_init(&sw); - /* Perform ram repair */ + /* Perform RAM repair */ reg = read32(&flow->ram_repair); reg |= req; write32(&flow->ram_repair, reg); diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h index 667d090118..dee7c7caab 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h @@ -951,9 +951,9 @@ struct sdram_params { /* Set if bit 6 select is greater than bit 7 select; uses aremc. spec packet SWIZZLE_BIT6_GT_BIT7 */ uint32_t SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot rom write */ + /* Specifies enable and offset for patched boot ROM write */ uint32_t BootRomPatchControl; - /* Specifies data for patched boot rom write */ + /* Specifies data for patched boot ROM write */ uint32_t BootRomPatchData; /* Specifies the value for MC_MTS_CARVEOUT_BOM */ diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 15477d6fe2..d3ac67b00f 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -1024,7 +1024,7 @@ void lp0_resume(void) * 1 : MAX77621 */ if (read32(pmc_scratch201_ptr) & PMIC_77621) - /* Set cpu rail 0.85V */ + /* Set CPU rail 0.85V */ i2c_send(MAX77621_I2C_ADDR, MAX77621_VOUT_DATA); else /* Enable GPIO5 on MAX77620 PMIC */ diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index c9ff35bfb5..9491570a0b 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -79,7 +79,7 @@ void romstage(void) cbmem_initialize_empty(); ccplex_cpu_prepare(); - printk(BIOS_INFO, "T210 romstage: cpu prepare done\n"); + printk(BIOS_INFO, "T210 romstage: CPU prepare done\n"); romstage_mainboard_init(); |