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authorYen Lin <yelin@nvidia.com>2015-05-29 14:36:19 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-07-09 00:09:08 +0200
commit13fb74927ee3d3527494622ca022010c519edd26 (patch)
tree3ddb3fa2674deca6415e3bfdd443e37206afe0d2 /src/soc/nvidia/tegra210
parentcc74221581f0b21dcf288532267da01680eb9cc1 (diff)
t210: i2c6: enable SOR_SAFE and DPAUX1 clocks for i2c6 to work
I2C6 controller needs SOR_SAFE and DPAUX1 clocks to work. These 2 clocks are mistakenly enabled by MBIST. MBIST fix will be submitted next, which will disable these 2 clocks as initial states. Enable these 2 clocks now so I2C6 will continue to work after MBIST fix. BUG=None BRANCH=None TEST=Tested on Smaug, make sure that panel shows display (I2C6 is used to turn on backlight) Change-Id: Id47453e784d53fd6831e8d19a8d57c04c4e1f82f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 83e935f100be85e1e831a3f9f16962304f7cd7d6 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Change-Id: If312881c94570066bdc54f0f5c48226e862bddc6 Original-Reviewed-on: https://chromium-review.googlesource.com/282415 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra210')
-rw-r--r--src/soc/nvidia/tegra210/i2c6.c3
-rw-r--r--src/soc/nvidia/tegra210/include/soc/clock.h2
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/i2c6.c b/src/soc/nvidia/tegra210/i2c6.c
index 915a5386e9..92130577c3 100644
--- a/src/soc/nvidia/tegra210/i2c6.c
+++ b/src/soc/nvidia/tegra210/i2c6.c
@@ -65,6 +65,9 @@ void soc_configure_i2c6pad(void)
*/
soc_configure_host1x();
+ /* enable SOR_SAFE and DPAUX_1 clocks */
+ clock_enable_y(CLK_Y_DPAUX1 | CLK_Y_SOR_SAFE);
+
/* Now we can write the I2C6 mux in DPAUX */
write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL);
/* Finally, power up the pads */
diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h
index ff9b282eaa..8564c83df3 100644
--- a/src/soc/nvidia/tegra210/include/soc/clock.h
+++ b/src/soc/nvidia/tegra210/include/soc/clock.h
@@ -158,7 +158,9 @@ enum {
CLK_X_SPARE = 0x1 << 0,
CLK_Y_APE = 0x1 << 6,
+ CLK_Y_DPAUX1 = 0x1 << 15,
CLK_Y_QSPI = 0x1 << 19,
+ CLK_Y_SOR_SAFE = 0x1 << 30,
};
enum {