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authorRavi Sarawadi <ravishankar.sarawadi@intel.com>2020-07-08 23:11:01 -0700
committerFurquan Shaikh <furquan@google.com>2020-07-25 04:46:44 +0000
commite4109ff54ff3268fe65739e8efe79b57e67d2e3c (patch)
treee65322e001ba95ec4c45473276ba18455e886f96 /src/soc/nvidia/tegra210/dsi.c
parent7cd8c79177ecf2143e878a8e2be916bfe222a8c7 (diff)
soc/intel/tigerlake: Update Pkg C-State latencies
Update to recommended C-state entry/exit latencies as per BWG(611569) Rev 0.8: section 4.5.3.2.2 BUG=none TEST=Boot to OS and check C-State latencies "cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}" Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43316 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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