diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-07-08 12:40:45 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-09 09:31:10 +0000 |
| commit | 39303d5d4960814fc606cce3a9ec10545faaef4b (patch) | |
| tree | 23e5acc814298022ac1c3314ceaae532d6303901 /src/soc/nvidia/tegra210/clock.c | |
| parent | fd051dc018346e5947d9d8733e269fc5020236ba (diff) | |
src/soc: Use "foo *bar" instead of "foo* bar"
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra210/clock.c')
| -rw-r--r-- | src/soc/nvidia/tegra210/clock.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 51cfc8b2c8..6ce2ba1291 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -654,7 +654,7 @@ void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg, write32(rst_dev_clr_reg, val); } -static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(clk_enb_l_set), CLK_RST_REG(clk_enb_h_set), CLK_RST_REG(clk_enb_u_set), @@ -664,7 +664,7 @@ static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(clk_enb_y_set), }; -static u32 * const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(clk_enb_l_clr), CLK_RST_REG(clk_enb_h_clr), CLK_RST_REG(clk_enb_u_clr), @@ -674,7 +674,7 @@ static u32 * const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(clk_enb_y_clr), }; -static u32 * const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(rst_dev_l_set), CLK_RST_REG(rst_dev_h_set), CLK_RST_REG(rst_dev_u_set), @@ -684,7 +684,7 @@ static u32 * const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(rst_dev_y_set), }; -static u32 * const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(rst_dev_l_clr), CLK_RST_REG(rst_dev_h_clr), CLK_RST_REG(rst_dev_u_clr), @@ -694,7 +694,7 @@ static u32 * const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(rst_dev_y_clr), }; -static void clock_write_regs(u32 * const regs[DEV_CONFIG_BLOCKS], +static void clock_write_regs(u32 *const regs[DEV_CONFIG_BLOCKS], u32 bits[DEV_CONFIG_BLOCKS]) { int i = 0; |