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authorFelix Singer <felixsinger@posteo.net>2024-01-09 00:19:19 +0100
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2024-01-09 23:23:24 +0000
commitd74ee60f71fd45449cd710a58a7f2ca9fae2ca49 (patch)
treef9d74da6de6a6ead013b886345c6db42b76f3744 /src/soc/nvidia/tegra210/clock.c
parenta4a65b202517871aee2f6b01c2530d25636c337d (diff)
soc/nvidia: Put static keyword at the beginning of declarations
In order to comply with the more recent style of declarations, put the static keyword at the beginning. Fixes following GCC error when the related flag is set: error: 'static' is not at beginning of declaration [-Werror=old-style-declaration] Change-Id: Ida683319f7a0c428a9e4808821075abdd9fcb504 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79856 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/clock.c')
-rw-r--r--src/soc/nvidia/tegra210/clock.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c
index 95507e3950..4433d7e177 100644
--- a/src/soc/nvidia/tegra210/clock.c
+++ b/src/soc/nvidia/tegra210/clock.c
@@ -27,7 +27,7 @@ enum {
PLL_MAX_INDEX,
};
-struct pll_reg_info {
+static const struct pll_reg_info {
u32 *base_reg;
u32 *lock_enb_reg;
u32 lock_enb_val;
@@ -40,7 +40,7 @@ struct pll_reg_info {
u32 kcp_shift:5; /* kcp bits location */
u32 kvco_shift:5; /* kvco bit location */
u32 rsvd:7;
-} static const pll_reg_table[] = {
+} pll_reg_table[] = {
[PLLX_INDEX] = { .base_reg = CLK_RST_REG(pllx_base),
.lock_enb_reg = CLK_RST_REG(pllx_misc),
.lock_enb_val = PLLPAXS_MISC_LOCK_ENABLE,
@@ -127,10 +127,10 @@ struct pll_fields {
* PLLM is set up dynamically by clock_sdram().
* PLLP is hardwired to 408 MHz in HW (unless we set BASE_OVRD).
*/
-struct {
+static struct {
int khz;
struct pll_fields plls[PLL_MAX_INDEX];
-} static osc_table[16] = {
+} osc_table[16] = {
[OSC_FREQ_12] = {
.khz = 12000,
.plls = {