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authorPatrick Georgi <pgeorgi@chromium.org>2015-06-22 19:41:29 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-06-30 21:43:01 +0200
commit40a3e321d4e8f2877de1700db67b8c7f7ea89820 (patch)
treeb8270b2ceb9e290d2e4e9a99868acb9cd335de6f /src/soc/nvidia/tegra210/ape.c
parent7f641e68f25c0b79960a97a6b265851c46298aae (diff)
nvidia/tegra210: add new SoC
This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/ape.c')
-rw-r--r--src/soc/nvidia/tegra210/ape.c55
1 files changed, 55 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/ape.c b/src/soc/nvidia/tegra210/ape.c
new file mode 100644
index 0000000000..b46c11ad6e
--- /dev/null
+++ b/src/soc/nvidia/tegra210/ape.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2015, NVIDIA CORPORATION.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <soc/clk_rst.h>
+#include <soc/clock.h>
+#include <soc/padconfig.h>
+#include <soc/power.h>
+
+static void enable_ape_periph_clocks(void)
+{
+ clock_enable(0, 0, 0, CLK_V_APB2APE, 0, 0, CLK_Y_APE);
+
+ /* Give clocks time to stabilize. */
+ udelay(IO_STABILIZATION_DELAY);
+}
+
+static void unreset_ape_periphs(void)
+{
+ clock_clr_reset(0, 0, 0, CLK_V_APB2APE, 0, 0, CLK_Y_APE);
+}
+
+/*
+ * Audio on Tegra210 requires some special init.
+ * The APE block must be unpowergated, and a couple of
+ * audio-based peripherals must be clocked and taken
+ * out of reset so that I2S/AXBAR/APB2APE registers can
+ * be configured to enable audio flow.
+ */
+
+void soc_configure_ape(void)
+{
+ power_ungate_partition(POWER_PARTID_APE);
+
+ enable_ape_periph_clocks();
+ remove_clamps(POWER_PARTID_APE);
+ unreset_ape_periphs();
+}