diff options
| author | Furquan Shaikh <furquan@google.com> | 2015-07-07 21:35:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-13 09:19:34 +0200 |
| commit | 3ae5044b7330ea4af0214b7db29749eed17f2e66 (patch) | |
| tree | b01c3bca82b607bf24ce4aee2fca29e6208d0c4f /src/soc/nvidia/tegra210/Kconfig | |
| parent | ccc55fdc6fae37a085e9f1a8a19a539728907ca1 (diff) | |
t210: Add TZDRAM_BASE param to BL31_MAKEARGS
1. Make TTB_SIZE Kconfig option
2. Add Kconfig option for maximum secure component size
3. Add check in Makefile to ensure that Trustzone area is big enough
to hold TTB and secure components
4. Calculate TZDRAM_BASE depending upon TTB_SIZE and TZ_CARVEOUT_SIZE
BUG=chrome-os-partner:42319
BRANCH=None
Change-Id: I9ceb46ceedc931826657e5a0f6fc2b1886526bf8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a425d4978a467b157ea5d71e600242ebf427b5bb
Original-Change-Id: I152a38830773d85aafab49c92cef945b7c4eb62c
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284074
Original-Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10878
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/Kconfig')
| -rw-r--r-- | src/soc/nvidia/tegra210/Kconfig | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 7aa932aa08..7aff588f41 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -102,6 +102,19 @@ config TRUSTZONE_CARVEOUT_SIZE_MB help Size of Trust Zone area in MiB to reserve in memory map. +config TTB_SIZE_MB + hex "Size of TTB" + default 0x4 + help + Maximum size of Translation Table Buffer in MiB. + +config SEC_COMPONENT_SIZE_MB + hex "Size of resident EL3 components" + default 0x10 + help + Maximum size of resident EL3 components in MiB including BL31 and + Secure OS. + # Default to 700MHz. This value is based on nv bootloader setting. config PLLX_KHZ int |